Overall: 2989/5551 fields covered

ADC1

0x50040000: Analog-to-Digital Converter

6/129 fields covered. Toggle Registers.

ISR

interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw
AWD3
rw
AWD2
rw
AWD1
rw
JEOS
rw
JEOC
rw
OVR
rw
EOS
rw
EOC
rw
EOSMP
rw
ADRDY
rw
Toggle Fields.

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw
AWD3IE
rw
AWD2IE
rw
AWD1IE
rw
JEOSIE
rw
JEOCIE
rw
OVRIE
rw
EOSIE
rw
EOCIE
rw
EOSMPIE
rw
ADRDYIE
rw
Toggle Fields.

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw
ADSTP
rw
JADSTART
rw
ADSTART
rw
ADDIS
rw
ADEN
rw
Toggle Fields.

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOFF
rw
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle Fields.

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

AUTOFF

Bit 15: AUTOFF.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

CFGR2

configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle Fields.

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sampling time selection.

SMP1

Bits 3-5: Channel 1 sampling time selection.

SMP2

Bits 6-8: Channel 2 sampling time selection.

SMP3

Bits 9-11: Channel 3 sampling time selection.

SMP4

Bits 12-14: Channel 4 sampling time selection.

SMP5

Bits 15-17: Channel 5 sampling time selection.

SMP6

Bits 18-20: Channel 6 sampling time selection.

SMP7

Bits 21-23: Channel 7 sampling time selection.

SMP8

Bits 24-26: Channel 8 sampling time selection.

SMP9

Bits 27-29: Channel 9 sampling time selection.

SMPR2

sample time register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sampling time selection.

SMP11

Bits 3-5: Channel 11 sampling time selection.

SMP12

Bits 6-8: Channel 12 sampling time selection.

SMP13

Bits 9-11: Channel 13 sampling time selection.

SMP14

Bits 12-14: Channel 14 sampling time selection.

SMP15

Bits 15-17: Channel 15 sampling time selection.

SMP16

Bits 18-20: Channel 16 sampling time selection.

SMP17

Bits 21-23: Channel 17 sampling time selection.

SMP18

Bits 24-26: Channel 18 sampling time selection.

TR1

watchdog threshold register 1

Offset: 0x20, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle Fields.

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle Fields.

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle Fields.

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw
SQ3
rw
SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw
SQ1
rw
L3
rw
Toggle Fields.

L3

Bits 0-3: L3.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw
SQ8
rw
SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw
SQ6
rw
SQ5
rw
Toggle Fields.

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw
SQ13
rw
SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw
SQ11
rw
SQ10
rw
Toggle Fields.

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
Toggle Fields.

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regularDATA
r
Toggle Fields.

regularDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw
JSQ3
rw
JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw
JSQ1
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle Fields.

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw
OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle Fields.

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw
OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle Fields.

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw
OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle Fields.

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw
OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle Fields.

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA1
r
Toggle Fields.

JDATA1

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA2
r
Toggle Fields.

JDATA2

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA3
r
Toggle Fields.

JDATA3

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA4
r
Toggle Fields.

JDATA4

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle Fields.

AWD2CH

Bits 1-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle Fields.

AWD3CH

Bits 1-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xB0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw
Toggle Fields.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xB4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle Fields.

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

ADC2

0x50040100: Analog-to-Digital Converter

6/129 fields covered. Toggle Registers.

ISR

interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw
AWD3
rw
AWD2
rw
AWD1
rw
JEOS
rw
JEOC
rw
OVR
rw
EOS
rw
EOC
rw
EOSMP
rw
ADRDY
rw
Toggle Fields.

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw
AWD3IE
rw
AWD2IE
rw
AWD1IE
rw
JEOSIE
rw
JEOCIE
rw
OVRIE
rw
EOSIE
rw
EOCIE
rw
EOSMPIE
rw
ADRDYIE
rw
Toggle Fields.

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
rw
ADSTP
rw
JADSTART
rw
ADSTART
rw
ADDIS
rw
ADEN
rw
Toggle Fields.

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

configuration register

Offset: 0xC, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTOFF
rw
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle Fields.

DMAEN

Bit 0: DMAEN.

DMACFG

Bit 1: DMACFG.

RES

Bits 3-4: RES.

ALIGN

Bit 5: ALIGN.

EXTSEL

Bits 6-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

AUTOFF

Bit 15: AUTOFF.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWDCH1CH

Bits 26-30: AWDCH1CH.

CFGR2

configuration register

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle Fields.

ROVSE

Bit 0: DMAEN.

JOVSE

Bit 1: DMACFG.

OVSR

Bits 2-4: RES.

OVSS

Bits 5-8: ALIGN.

TOVS

Bit 9: EXTSEL.

ROVSM

Bit 10: EXTEN.

SMPR1

sample time register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw
SMP8
rw
SMP7
rw
SMP6
rw
SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw
SMP4
rw
SMP3
rw
SMP2
rw
SMP1
rw
SMP0
rw
Toggle Fields.

SMP0

Bits 0-2: Channel 0 sampling time selection.

SMP1

Bits 3-5: Channel 1 sampling time selection.

SMP2

Bits 6-8: Channel 2 sampling time selection.

SMP3

Bits 9-11: Channel 3 sampling time selection.

SMP4

Bits 12-14: Channel 4 sampling time selection.

SMP5

Bits 15-17: Channel 5 sampling time selection.

SMP6

Bits 18-20: Channel 6 sampling time selection.

SMP7

Bits 21-23: Channel 7 sampling time selection.

SMP8

Bits 24-26: Channel 8 sampling time selection.

SMP9

Bits 27-29: Channel 9 sampling time selection.

SMPR2

sample time register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP18
rw
SMP17
rw
SMP16
rw
SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw
SMP14
rw
SMP13
rw
SMP12
rw
SMP11
rw
SMP10
rw
Toggle Fields.

SMP10

Bits 0-2: Channel 10 sampling time selection.

SMP11

Bits 3-5: Channel 11 sampling time selection.

SMP12

Bits 6-8: Channel 12 sampling time selection.

SMP13

Bits 9-11: Channel 13 sampling time selection.

SMP14

Bits 12-14: Channel 14 sampling time selection.

SMP15

Bits 15-17: Channel 15 sampling time selection.

SMP16

Bits 18-20: Channel 16 sampling time selection.

SMP17

Bits 21-23: Channel 17 sampling time selection.

SMP18

Bits 24-26: Channel 18 sampling time selection.

TR1

watchdog threshold register 1

Offset: 0x20, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle Fields.

LT1

Bits 0-11: LT1.

HT1

Bits 16-27: HT1.

TR2

watchdog threshold register

Offset: 0x24, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle Fields.

LT2

Bits 0-7: LT2.

HT2

Bits 16-23: HT2.

TR3

watchdog threshold register 3

Offset: 0x28, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle Fields.

LT3

Bits 0-7: LT3.

HT3

Bits 16-23: HT3.

SQR1

regular sequence register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw
SQ3
rw
SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw
SQ1
rw
L3
rw
Toggle Fields.

L3

Bits 0-3: L3.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

regular sequence register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw
SQ8
rw
SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw
SQ6
rw
SQ5
rw
Toggle Fields.

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

regular sequence register 3

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw
SQ13
rw
SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw
SQ11
rw
SQ10
rw
Toggle Fields.

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

regular sequence register 4

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw
SQ15
rw
Toggle Fields.

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

regular Data Register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
regularDATA
r
Toggle Fields.

regularDATA

Bits 0-15: regularDATA.

JSQR

injected sequence register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw
JSQ3
rw
JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw
JSQ1
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle Fields.

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-5: JEXTSEL.

JEXTEN

Bits 6-7: JEXTEN.

JSQ1

Bits 8-12: JSQ1.

JSQ2

Bits 14-18: JSQ2.

JSQ3

Bits 20-24: JSQ3.

JSQ4

Bits 26-30: JSQ4.

OFR1

offset register 1

Offset: 0x60, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET1_EN
rw
OFFSET1_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle Fields.

OFFSET1

Bits 0-11: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

OFFSET1_EN

Bit 31: OFFSET1_EN.

OFR2

offset register 2

Offset: 0x64, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET2_EN
rw
OFFSET2_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle Fields.

OFFSET2

Bits 0-11: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

OFFSET2_EN

Bit 31: OFFSET2_EN.

OFR3

offset register 3

Offset: 0x68, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET3_EN
rw
OFFSET3_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle Fields.

OFFSET3

Bits 0-11: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

OFFSET3_EN

Bit 31: OFFSET3_EN.

OFR4

offset register 4

Offset: 0x6C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET4_EN
rw
OFFSET4_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle Fields.

OFFSET4

Bits 0-11: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

OFFSET4_EN

Bit 31: OFFSET4_EN.

JDR1

injected data register 1

Offset: 0x80, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA1
r
Toggle Fields.

JDATA1

Bits 0-15: JDATA1.

JDR2

injected data register 2

Offset: 0x84, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA2
r
Toggle Fields.

JDATA2

Bits 0-15: JDATA2.

JDR3

injected data register 3

Offset: 0x88, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA3
r
Toggle Fields.

JDATA3

Bits 0-15: JDATA3.

JDR4

injected data register 4

Offset: 0x8C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA4
r
Toggle Fields.

JDATA4

Bits 0-15: JDATA4.

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle Fields.

AWD2CH

Bits 1-18: AWD2CH.

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle Fields.

AWD3CH

Bits 1-18: AWD3CH.

DIFSEL

Differential Mode Selection Register 2

Offset: 0xB0, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL_16_18
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL_1_15
rw
Toggle Fields.

DIFSEL_1_15

Bits 1-15: Differential mode for channels 15 to 1.

DIFSEL_16_18

Bits 16-18: Differential mode for channels 18 to 16.

CALFACT

Calibration Factors

Offset: 0xB4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle Fields.

CALFACT_S

Bits 0-6: CALFACT_S.

CALFACT_D

Bits 16-22: CALFACT_D.

ADC_Common

1342440192: ADC common registers

24/33 fields covered. Toggle Registers.

CSR

ADC common status register

Offset: 0x0, reset: 0, access: read-only

22/22 fields covered.

ADRDY_MST

Bit 0: master ADC ready.

EOSMP_MST

Bit 1: End of Sampling phase flag of the master ADC.

EOC_MST

Bit 2: End of regular conversion flag of the master ADC.

EOS_MST

Bit 3: End of regular sequence flag of the master ADC.

OVR_MST

Bit 4: Overrun flag of the master ADC.

JEOC_MST

Bit 5: End of injected conversion flag of the master ADC.

JEOS_MST

Bit 6: End of injected sequence flag of the master ADC.

AWD1_MST

Bit 7: Analog watchdog 1 flag of the master ADC.

AWD2_MST

Bit 8: Analog watchdog 2 flag of the master ADC.

AWD3_MST

Bit 9: Analog watchdog 3 flag of the master ADC.

JQOVF_MST

Bit 10: Injected Context Queue Overflow flag of the master ADC.

ADRDY_SLV

Bit 16: Slave ADC ready.

EOSMP_SLV

Bit 17: End of Sampling phase flag of the slave ADC.

EOC_SLV

Bit 18: End of regular conversion flag of the slave ADC.

EOS_SLV

Bit 19: End of regular sequence flag of the slave ADC.

OVR_SLV

Bit 20: Overrun flag of the slave ADC.

JEOC_SLV

Bit 21: End of injected conversion flag of the slave ADC.

JEOS_SLV

Bit 22: End of injected sequence flag of the slave ADC.

AWD1_SLV

Bit 23: Analog watchdog 1 flag of the slave ADC.

AWD2_SLV

Bit 24: Analog watchdog 2 flag of the slave ADC.

AWD3_SLV

Bit 25: Analog watchdog 3 flag of the slave ADC.

JQOVF_SLV

Bit 26: Injected Context Queue Overflow flag of the slave ADC.

CCR

ADC common control register

Offset: 0x8, reset: 0, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18SEL
rw
CH17SEL
rw
VREFEN
rw
PRESC
rw
CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw
DMACFG
rw
DELAY
rw
DUAL
rw
Toggle Fields.

DUAL

Bits 0-4: Dual ADC mode selection.

DELAY

Bits 8-11: Delay between 2 sampling phases.

DMACFG

Bit 13: DMA configuration (for dual ADC mode).

MDMA

Bits 14-15: Direct memory access mode for dual ADC mode.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: Vrefint enable.

CH17SEL

Bit 23: CH17 selection (temperature).

CH18SEL

Bit 24: CH18 selection (Vbat).

CDR

ADC common regular data register for dual mode

Offset: 0x12, reset: 0, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle Fields.

RDATA_MST

Bits 0-15: Regular data of the master ADC.

RDATA_SLV

Bits 16-31: Regular data of the slave ADC.

AES

0x50060000: Advanced encryption standard hardware accelerator

4/23 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAOUTEN
rw
DMAINEN
rw
ERRIE
rw
CCFIE
rw
ERRC
rw
CCFC
rw
CHMOD
rw
MODE
rw
DATATYPE
rw
EN
rw
Toggle Fields.

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD

Bits 5-6: AES chaining mode.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

SR

status register

Offset: 0x4, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRERR
r
RDERR
r
CCF
r
Toggle Fields.

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

DINR

data input register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DINR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DINR
rw
Toggle Fields.

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_DOUTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_DOUTR
r
Toggle Fields.

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR0
rw
Toggle Fields.

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR1
rw
Toggle Fields.

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR2
rw
Toggle Fields.

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_KEYR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_KEYR3
rw
Toggle Fields.

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR0
rw
Toggle Fields.

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR1
rw
Toggle Fields.

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR2
rw
Toggle Fields.

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AES_IVR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AES_IVR3
rw
Toggle Fields.

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

CAN1

0x40006400: Controller area network

57/161 fields covered. Toggle Registers.

MCR

master control register

Offset: 0x0, reset: 0x00010002, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET
rw
TTCM
rw
ABOM
rw
AWUM
rw
NART
rw
RFLM
rw
TXFP
rw
SLEEP
rw
INRQ
rw
Toggle Fields.

INRQ

Bit 0: INRQ.

SLEEP

Bit 1: SLEEP.

TXFP

Bit 2: TXFP.

RFLM

Bit 3: RFLM.

NART

Bit 4: NART.

AWUM

Bit 5: AWUM.

ABOM

Bit 6: ABOM.

TTCM

Bit 7: TTCM.

RESET

Bit 15: RESET.

DBF

Bit 16: DBF.

MSR

master status register

Offset: 0x4, reset: 0x00000C02, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r
SAMP
r
RXM
r
TXM
r
SLAKI
rw
WKUI
rw
ERRI
rw
SLAK
r
INAK
r
Toggle Fields.

INAK

Bit 0: INAK.

SLAK

Bit 1: SLAK.

ERRI

Bit 2: ERRI.

WKUI

Bit 3: WKUI.

SLAKI

Bit 4: SLAKI.

TXM

Bit 8: TXM.

RXM

Bit 9: RXM.

SAMP

Bit 10: SAMP.

RX

Bit 11: RX.

TSR

transmit status register

Offset: 0x8, reset: 0x1C000000, access: Unspecified

7/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOW2
r
LOW1
r
LOW0
r
TME2
r
TME1
r
TME0
r
CODE
r
ABRQ2
rw
TERR2
rw
ALST2
rw
TXOK2
rw
RQCP2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRQ1
rw
TERR1
rw
ALST1
rw
TXOK1
rw
RQCP1
rw
ABRQ0
rw
TERR0
rw
ALST0
rw
TXOK0
rw
RQCP0
rw
Toggle Fields.

RQCP0

Bit 0: RQCP0.

TXOK0

Bit 1: TXOK0.

ALST0

Bit 2: ALST0.

TERR0

Bit 3: TERR0.

ABRQ0

Bit 7: ABRQ0.

RQCP1

Bit 8: RQCP1.

TXOK1

Bit 9: TXOK1.

ALST1

Bit 10: ALST1.

TERR1

Bit 11: TERR1.

ABRQ1

Bit 15: ABRQ1.

RQCP2

Bit 16: RQCP2.

TXOK2

Bit 17: TXOK2.

ALST2

Bit 18: ALST2.

TERR2

Bit 19: TERR2.

ABRQ2

Bit 23: ABRQ2.

CODE

Bits 24-25: CODE.

TME0

Bit 26: Lowest priority flag for mailbox 0.

TME1

Bit 27: Lowest priority flag for mailbox 1.

TME2

Bit 28: Lowest priority flag for mailbox 2.

LOW0

Bit 29: Lowest priority flag for mailbox 0.

LOW1

Bit 30: Lowest priority flag for mailbox 1.

LOW2

Bit 31: Lowest priority flag for mailbox 2.

RF%sR

receive FIFO 0 register

Offset: 0xC, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFOM
rw
FOVR
rw
FULL
rw
FMP
r
Toggle Fields.

FMP

Bits 0-1: FMP0.

FULL

Bit 3: FULL0.

Allowed values:
0: NotFull: FIFO x is not full
1: Full: FIFO x is full

FOVR

Bit 4: FOVR0.

Allowed values:
0: NoOverrun: No FIFO x overrun
1: Overrun: FIFO x overrun

RFOM

Bit 5: RFOM0.

Allowed values:
1: Release: Set by software to release the output mailbox of the FIFO

IER

interrupt enable register

Offset: 0x14, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLKIE
rw
WKUIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
LECIE
rw
BOFIE
rw
EPVIE
rw
EWGIE
rw
FOVIE1
rw
FFIE1
rw
FMPIE1
rw
FOVIE0
rw
FFIE0
rw
FMPIE0
rw
TMEIE
rw
Toggle Fields.

TMEIE

Bit 0: TMEIE.

Allowed values:
0: Disabled: No interrupt when RQCPx bit is set
1: Enabled: Interrupt generated when RQCPx bit is set

FMPIE0

Bit 1: FMPIE0.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE0

Bit 2: FFIE0.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE0

Bit 3: FOVIE0.

Allowed values:
0: Disabled: No interrupt when FOVR bit is set
1: Enabled: Interrupt generated when FOVR bit is set

FMPIE1

Bit 4: FMPIE1.

Allowed values:
0: Disabled: No interrupt generated when state of FMP[1:0] bits are not 00b
1: Enabled: Interrupt generated when state of FMP[1:0] bits are not 00b

FFIE1

Bit 5: FFIE1.

Allowed values:
0: Disabled: No interrupt when FULL bit is set
1: Enabled: Interrupt generated when FULL bit is set

FOVIE1

Bit 6: FOVIE1.

Allowed values:
0: Disabled: No interrupt when FOVR is set
1: Enabled: Interrupt generation when FOVR is set

EWGIE

Bit 8: EWGIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EWGF is set
1: Enabled: ERRI bit will be set when EWGF is set

EPVIE

Bit 9: EPVIE.

Allowed values:
0: Disabled: ERRI bit will not be set when EPVF is set
1: Enabled: ERRI bit will be set when EPVF is set

BOFIE

Bit 10: BOFIE.

Allowed values:
0: Disabled: ERRI bit will not be set when BOFF is set
1: Enabled: ERRI bit will be set when BOFF is set

LECIE

Bit 11: LECIE.

Allowed values:
0: Disabled: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection
1: Enabled: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection

ERRIE

Bit 15: ERRIE.

Allowed values:
0: Disabled: No interrupt will be generated when an error condition is pending in the CAN_ESR
1: Enabled: An interrupt will be generation when an error condition is pending in the CAN_ESR

WKUIE

Bit 16: WKUIE.

Allowed values:
0: Disabled: No interrupt when WKUI is set
1: Enabled: Interrupt generated when WKUI bit is set

SLKIE

Bit 17: SLKIE.

Allowed values:
0: Disabled: No interrupt when SLAKI bit is set
1: Enabled: Interrupt generated when SLAKI bit is set

ESR

interrupt enable register

Offset: 0x18, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC
r
TEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEC
rw
BOFF
r
EPVF
r
EWGF
r
Toggle Fields.

EWGF

Bit 0: EWGF.

EPVF

Bit 1: EPVF.

BOFF

Bit 2: BOFF.

LEC

Bits 4-6: LEC.

Allowed values:
0: NoError: No Error
1: Stuff: Stuff Error
2: Form: Form Error
3: Ack: Acknowledgment Error
4: BitRecessive: Bit recessive Error
5: BitDominant: Bit dominant Error
6: Crc: CRC Error
7: Custom: Set by software

TEC

Bits 16-23: TEC.

REC

Bits 24-31: REC.

BTR

bit timing register

Offset: 0x1C, reset: 0x00000000, access: read-write

2/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SILM
rw
LBKM
rw
SJW
rw
TS2
rw
TS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRP
rw
Toggle Fields.

BRP

Bits 0-9: BRP.

TS1

Bits 16-19: TS1.

TS2

Bits 20-22: TS2.

SJW

Bits 24-25: SJW.

LBKM

Bit 30: LBKM.

Allowed values:
0: Disabled: Loop Back Mode disabled
1: Enabled: Loop Back Mode enabled

SILM

Bit 31: SILM.

Allowed values:
0: Normal: Normal operation
1: Silent: Silent Mode

FMR

filter master register

Offset: 0x200, reset: 0x2A1C0E01, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FINIT
rw
Toggle Fields.

FINIT

Bit 0: Filter initialization mode.

FM1R

filter mode register

Offset: 0x204, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FBM13
rw
FBM12
rw
FBM11
rw
FBM10
rw
FBM9
rw
FBM8
rw
FBM7
rw
FBM6
rw
FBM5
rw
FBM4
rw
FBM3
rw
FBM2
rw
FBM1
rw
FBM0
rw
Toggle Fields.

FBM0

Bit 0: Filter mode.

FBM1

Bit 1: Filter mode.

FBM2

Bit 2: Filter mode.

FBM3

Bit 3: Filter mode.

FBM4

Bit 4: Filter mode.

FBM5

Bit 5: Filter mode.

FBM6

Bit 6: Filter mode.

FBM7

Bit 7: Filter mode.

FBM8

Bit 8: Filter mode.

FBM9

Bit 9: Filter mode.

FBM10

Bit 10: Filter mode.

FBM11

Bit 11: Filter mode.

FBM12

Bit 12: Filter mode.

FBM13

Bit 13: Filter mode.

FS1R

filter scale register

Offset: 0x20C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSC13
rw
FSC12
rw
FSC11
rw
FSC10
rw
FSC9
rw
FSC8
rw
FSC7
rw
FSC6
rw
FSC5
rw
FSC4
rw
FSC3
rw
FSC2
rw
FSC1
rw
FSC0
rw
Toggle Fields.

FSC0

Bit 0: Filter scale configuration.

FSC1

Bit 1: Filter scale configuration.

FSC2

Bit 2: Filter scale configuration.

FSC3

Bit 3: Filter scale configuration.

FSC4

Bit 4: Filter scale configuration.

FSC5

Bit 5: Filter scale configuration.

FSC6

Bit 6: Filter scale configuration.

FSC7

Bit 7: Filter scale configuration.

FSC8

Bit 8: Filter scale configuration.

FSC9

Bit 9: Filter scale configuration.

FSC10

Bit 10: Filter scale configuration.

FSC11

Bit 11: Filter scale configuration.

FSC12

Bit 12: Filter scale configuration.

FSC13

Bit 13: Filter scale configuration.

FFA1R

filter FIFO assignment register

Offset: 0x214, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FFA13
rw
FFA12
rw
FFA11
rw
FFA10
rw
FFA9
rw
FFA8
rw
FFA7
rw
FFA6
rw
FFA5
rw
FFA4
rw
FFA3
rw
FFA2
rw
FFA1
rw
FFA0
rw
Toggle Fields.

FFA0

Bit 0: Filter FIFO assignment for filter 0.

FFA1

Bit 1: Filter FIFO assignment for filter 1.

FFA2

Bit 2: Filter FIFO assignment for filter 2.

FFA3

Bit 3: Filter FIFO assignment for filter 3.

FFA4

Bit 4: Filter FIFO assignment for filter 4.

FFA5

Bit 5: Filter FIFO assignment for filter 5.

FFA6

Bit 6: Filter FIFO assignment for filter 6.

FFA7

Bit 7: Filter FIFO assignment for filter 7.

FFA8

Bit 8: Filter FIFO assignment for filter 8.

FFA9

Bit 9: Filter FIFO assignment for filter 9.

FFA10

Bit 10: Filter FIFO assignment for filter 10.

FFA11

Bit 11: Filter FIFO assignment for filter 11.

FFA12

Bit 12: Filter FIFO assignment for filter 12.

FFA13

Bit 13: Filter FIFO assignment for filter 13.

FA1R

filter activation register

Offset: 0x21C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FACT13
rw
FACT12
rw
FACT11
rw
FACT10
rw
FACT9
rw
FACT8
rw
FACT7
rw
FACT6
rw
FACT5
rw
FACT4
rw
FACT3
rw
FACT2
rw
FACT1
rw
FACT0
rw
Toggle Fields.

FACT0

Bit 0: Filter active.

FACT1

Bit 1: Filter active.

FACT2

Bit 2: Filter active.

FACT3

Bit 3: Filter active.

FACT4

Bit 4: Filter active.

FACT5

Bit 5: Filter active.

FACT6

Bit 6: Filter active.

FACT7

Bit 7: Filter active.

FACT8

Bit 8: Filter active.

FACT9

Bit 9: Filter active.

FACT10

Bit 10: Filter active.

FACT11

Bit 11: Filter active.

FACT12

Bit 12: Filter active.

FACT13

Bit 13: Filter active.

COMP

0x40010200: Comparator

2/25 fields covered. Toggle Registers.

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, reset: 0x0, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w
COMP1_VALUE
r
COMP1_INMESEL
rw
COMP1_SCALEN
rw
COMP1_BRGEN
rw
COMP1_BLANKING
rw
COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw
COMP1_INPSEL
rw
COMP1_INMSEL
rw
COMP1_PWRMODE
rw
COMP1_EN
rw
Toggle Fields.

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bits 7-8: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_INMESEL

Bits 25-26: comparator 1 input minus extended selection bits.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, reset: 0x0, access: Unspecified

1/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2_LOCK
w
COMP2_VALUE
r
COMP2_INMESEL
rw
COMP2_SCALEN
rw
COMP2_BRGEN
rw
COMP2_BLANKING
rw
COMP2_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2_POLARITY
rw
COMP2_WINMODE
rw
COMP2_INPSEL
rw
COMP2_INMSEL
rw
COMP2_PWRMODE
rw
COMP2_EN
rw
Toggle Fields.

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bits 7-8: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_INMESEL

Bits 25-26: comparator 2 input minus extended selection bits.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

9/10 fields covered. Toggle Registers.

DR16

Data register - half-word sized

Offset: 0x0, reset: 65535, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR16
rw
Toggle Fields.

DR16

Bits 0-15: Data register bits.

Allowed values: 0-65535

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle Fields.

IDR

Bits 0-7: General-purpose 8-bit data register bits.

Allowed values: 0-255

CR

Control register

Offset: 0x8, reset: 0x00000000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw
REV_IN
rw
POLYSIZE
rw
RESET
w
Toggle Fields.

RESET

Bit 0: RESET bit.

Allowed values:
1: Reset: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF

POLYSIZE

Bits 3-4: Polynomial size.

Allowed values:
0: Polysize32: 32-bit polynomial
1: Polysize16: 16-bit polynomial
2: Polysize8: 8-bit polynomial
3: Polysize7: 7-bit polynomial

REV_IN

Bits 5-6: Reverse input data.

Allowed values:
0: Normal: Bit order not affected
1: Byte: Bit reversal done by byte
2: HalfWord: Bit reversal done by half-word
3: Word: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data.

Allowed values:
0: Normal: Bit order not affected
1: Reversed: Bit reversed output

INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
Toggle Fields.

INIT

Bits 0-31: Programmable initial CRC value.

Allowed values: 0-4294967295

POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Polynomialcoefficients
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Polynomialcoefficients
rw
Toggle Fields.

Polynomialcoefficients

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00002000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
SWSYNC
rw
AUTOTRIMEN
rw
CEN
rw
ESYNCIE
rw
ERRIE
rw
SYNCWARNIE
rw
SYNCOKIE
rw
Toggle Fields.

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-13: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw
SYNCSRC
rw
SYNCDIV
rw
FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle Fields.

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r
TRIMOVF
r
SYNCMISS
r
SYNCERR
r
ESYNCF
r
ERRF
r
SYNCWARNF
r
SYNCOKF
r
Toggle Fields.

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw
ERRC
rw
SYNCWARNC
rw
SYNCOKC
rw
Toggle Fields.

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DAC1

0x40007400: Digital-to-analog converter

6/48 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw
DMAUDRIE2
rw
DMAEN2
rw
MAMP2
rw
WAVE2
rw
TSEL2
rw
TEN2
rw
EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEN1
rw
DMAUDRIE1
rw
DMAEN1
rw
MAMP1
rw
WAVE1
rw
TSEL1
rw
TEN1
rw
EN1
rw
Toggle Fields.

EN1

Bit 0: DAC channel1 enable.

TEN1

Bit 2: DAC channel1 trigger enable.

TSEL1

Bits 3-5: DAC channel1 trigger selection.

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable.

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

CEN1

Bit 14: DAC Channel 1 calibration enable.

EN2

Bit 16: DAC channel2 enable.

TEN2

Bit 18: DAC channel2 trigger enable.

TSEL2

Bits 19-21: DAC channel2 trigger selection.

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector.

DMAEN2

Bit 28: DAC channel2 DMA enable.

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable.

CEN2

Bit 30: DAC Channel 2 calibration enable.

SWTRIGR

software trigger register

Offset: 0x4, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w
SWTRIG1
w
Toggle Fields.

SWTRIG1

Bit 0: DAC channel1 software trigger.

SWTRIG2

Bit 1: DAC channel2 software trigger.

DHR12R1

channel1 12-bit right-aligned data holding register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DHR12L1

channel1 12-bit left-aligned data holding register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DHR8R1

channel1 8-bit right-aligned data holding register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DHR12R2

channel2 12-bit right aligned data holding register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data.

DHR12L2

channel2 12-bit left aligned data holding register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data.

DHR8R2

channel2 8-bit right-aligned data holding register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle Fields.

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data.

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
DACC1DHR
rw
Toggle Fields.

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

DOR1

channel1 data output register

Offset: 0x2C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle Fields.

DACC1DOR

Bits 0-11: DAC channel1 data output.

DOR2

channel2 data output register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle Fields.

DACC2DOR

Bits 0-11: DAC channel2 data output.

SR

status register

Offset: 0x34, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r
CAL_FLAG2
r
DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r
CAL_FLAG1
r
DMAUDR1
rw
Toggle Fields.

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag.

CAL_FLAG1

Bit 14: DAC Channel 1 calibration offset status.

BWST1

Bit 15: DAC Channel 1 busy writing sample time flag.

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag.

CAL_FLAG2

Bit 30: DAC Channel 2 calibration offset status.

BWST2

Bit 31: DAC Channel 2 busy writing sample time flag.

CCR

calibration control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle Fields.

OTRIM1

Bits 0-4: DAC Channel 1 offset trimming value.

OTRIM2

Bits 16-20: DAC Channel 2 offset trimming value.

MCR

mode control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle Fields.

MODE1

Bits 0-2: DAC Channel 1 mode.

MODE2

Bits 16-18: DAC Channel 2 mode.

SHSR1

Sample and Hold sample time register 1

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle Fields.

TSAMPLE1

Bits 0-9: DAC Channel 1 sample Time.

SHSR2

Sample and Hold sample time register 2

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle Fields.

TSAMPLE2

Bits 0-9: DAC Channel 2 sample Time.

SHHR

Sample and Hold hold time register

Offset: 0x48, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle Fields.

THOLD1

Bits 0-9: DAC Channel 1 hold Time.

THOLD2

Bits 16-25: DAC Channel 2 hold time.

SHRR

Sample and Hold refresh time register

Offset: 0x4C, reset: 0x00000001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle Fields.

TREFRESH1

Bits 0-7: DAC Channel 1 refresh Time.

TREFRESH2

Bits 16-23: DAC Channel 2 refresh Time.

DBGMCU

0xE0042000: MCU debug component

2/22 fields covered. Toggle Registers.

IDCODE

DBGMCU_IDCODE

Offset: 0x0, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle Fields.

DEV_ID

Bits 0-11: Device identifier.

REV_ID

Bits 16-31: Revision identifie.

CR

Debug MCU configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw
TRACE_IOEN
rw
DBG_STANDBY
rw
DBG_STOP
rw
DBG_SLEEP
rw
Toggle Fields.

DBG_SLEEP

Bit 0: Debug Sleep mode.

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby mode.

TRACE_IOEN

Bit 5: Trace pin assignment control.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1FZR1

Debug MCU APB1 freeze register1

Offset: 0x8, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIM1_STOP
rw
DBG_CAN_STOP
rw
DBG_I2C3_STOP
rw
DBG_I2C2_STOP
rw
DBG_I2C1_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_IWDG_STOP
rw
DBG_WWDG_STOP
rw
DBG_RTC_STOP
rw
DBG_TIM7_STOP
rw
DBG_TIM6_STOP
rw
DBG_TIM2_STOP
rw
Toggle Fields.

DBG_TIM2_STOP

Bit 0: TIM2 counter stopped when core is halted.

DBG_TIM6_STOP

Bit 4: TIM6 counter stopped when core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_WWDG_STOP

Bit 11: Window watchdog counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: Independent watchdog counter stopped when core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout counter stopped when core is halted.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout counter stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout counter stopped when core is halted.

DBG_CAN_STOP

Bit 25: bxCAN stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1FZR2

Debug MCU APB1 freeze register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM2_STOP
rw
Toggle Fields.

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

APB2FZR

Debug MCU APB2 freeze register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM16_STOP
rw
DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM1_STOP
rw
Toggle Fields.

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM15_STOP

Bit 16: TIM15 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DFSDM

0x40016000: Digital filter for sigma delta modulators

21/105 fields covered. Toggle Registers.

CR2

control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle Fields.

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

CFGR2

channel configuration y register

Offset: 0x4, reset: 0x0, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle Fields.

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

ISR

interrupt and status register

Offset: 0x8, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle Fields.

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

ICR

interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle Fields.

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

JCHGR

injected channel group selection register

Offset: 0x10, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle Fields.

JCHG

Bits 0-7: Injected channel group selection.

FCR

filter control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle Fields.

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

JDATAR

data register for injected group

Offset: 0x18, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle Fields.

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

RDATAR

data register for the regular channel

Offset: 0x1C, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle Fields.

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

AWHTR

analog watchdog high threshold register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle Fields.

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

AWLTR

analog watchdog low threshold register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle Fields.

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

AWSR

analog watchdog status register

Offset: 0x28, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle Fields.

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

AWCFR

analog watchdog clear flag register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle Fields.

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

EXMAX

Extremes detector maximum register

Offset: 0x30, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle Fields.

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

EXMIN

Extremes detector minimum register

Offset: 0x34, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle Fields.

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

CNVTIMR

conversion timer register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle Fields.

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DFSDM0_CR2

control register 2

Offset: 0x104, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle Fields.

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM1_CR2

control register 2

Offset: 0x204, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle Fields.

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM2_CR2

control register 2

Offset: 0x304, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle Fields.

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DFSDM3_CR2

control register 2

Offset: 0x404, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle Fields.

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

DMA1

0x40020000: Direct memory access controller

154/168 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r
HTIF7
r
TCIF7
r
GIF7
r
TEIF6
r
HTIF6
r
TCIF6
r
GIF6
r
TEIF5
r
HTIF5
r
TCIF5
r
GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r
HTIF4
r
TCIF4
r
GIF4
r
TEIF3
r
HTIF3
r
TCIF3
r
GIF3
r
TEIF2
r
HTIF2
r
TCIF2
r
GIF2
r
TEIF1
r
HTIF1
r
TCIF1
r
GIF1
r
Toggle Fields.

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
w
CHTIF7
w
CTCIF7
w
CGIF7
w
CTEIF6
w
CHTIF6
w
CTCIF6
w
CGIF6
w
CTEIF5
w
CHTIF5
w
CTCIF5
w
CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w
CHTIF4
w
CTCIF4
w
CGIF4
w
CTEIF3
w
CHTIF3
w
CTCIF3
w
CGIF3
w
CTEIF2
w
CHTIF2
w
CTCIF2
w
CGIF2
w
CTEIF1
w
CHTIF1
w
CTCIF1
w
CGIF1
w
Toggle Fields.

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR1

channel x number of data register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR2

channel x number of data register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR3

channel x number of data register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR4

channel x number of data register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR5

channel x number of data register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR6

channel x number of data register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR7

channel x number of data register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CSELR

channel selection register

Offset: 0xA8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C7S
rw
C6S
rw
C5S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4S
rw
C3S
rw
C2S
rw
C1S
rw
Toggle Fields.

C1S

Bits 0-3: DMA channel 1 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C2S

Bits 4-7: DMA channel 2 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C3S

Bits 8-11: DMA channel 3 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C4S

Bits 12-15: DMA channel 4 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C5S

Bits 16-19: DMA channel 5 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C6S

Bits 20-23: DMA channel 6 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C7S

Bits 24-27: DMA channel 7 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

DMA2

0x40020400: Direct memory access controller

154/168 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF7
r
HTIF7
r
TCIF7
r
GIF7
r
TEIF6
r
HTIF6
r
TCIF6
r
GIF6
r
TEIF5
r
HTIF5
r
TCIF5
r
GIF5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4
r
HTIF4
r
TCIF4
r
GIF4
r
TEIF3
r
HTIF3
r
TCIF3
r
GIF3
r
TEIF2
r
HTIF2
r
TCIF2
r
GIF2
r
TEIF1
r
HTIF1
r
TCIF1
r
GIF1
r
Toggle Fields.

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTEIF7
w
CHTIF7
w
CTCIF7
w
CGIF7
w
CTEIF6
w
CHTIF6
w
CTCIF6
w
CGIF6
w
CTEIF5
w
CHTIF5
w
CTCIF5
w
CGIF5
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTEIF4
w
CHTIF4
w
CTCIF4
w
CGIF4
w
CTEIF3
w
CHTIF3
w
CTCIF3
w
CGIF3
w
CTEIF2
w
CHTIF2
w
CTCIF2
w
CGIF2
w
CTEIF1
w
CHTIF1
w
CTCIF1
w
CGIF1
w
Toggle Fields.

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR1

channel x number of data register

Offset: 0xC, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR2

channel x number of data register

Offset: 0x20, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR3

channel x number of data register

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR4

channel x number of data register

Offset: 0x48, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR5

channel x number of data register

Offset: 0x5C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR6

channel x number of data register

Offset: 0x70, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle Fields.

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

CNDTR7

channel x number of data register

Offset: 0x84, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

Allowed values: 0-65535

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle Fields.

MA

Bits 0-31: Memory address.

CSELR

channel selection register

Offset: 0xA8, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C7S
rw
C6S
rw
C5S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4S
rw
C3S
rw
C2S
rw
C1S
rw
Toggle Fields.

C1S

Bits 0-3: DMA channel 1 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C2S

Bits 4-7: DMA channel 2 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C3S

Bits 8-11: DMA channel 3 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C4S

Bits 12-15: DMA channel 4 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C5S

Bits 16-19: DMA channel 5 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C6S

Bits 20-23: DMA channel 6 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

C7S

Bits 24-27: DMA channel 7 selection.

Allowed values:
0: NoMapping: Default mapping
1: Map1: Mapping 1
2: Map2: Mapping 2
3: Map3: Mapping 3
4: Map4: Mapping 4
5: Map5: Mapping 5
6: Map6: Mapping 6
7: Map7: Mapping 7
8: Map8: Mapping 8
9: Map9: Mapping 9
10: Map10: Mapping 10
11: Map11: Mapping 11
12: Map12: Mapping 12
13: Map13: Mapping 13
14: Map14: Mapping 14
15: Map15: Mapping 15

EXTI

0x40010400: External interrupt/event controller

184/184 fields covered. Toggle Registers.

IMR1

Interrupt mask register

Offset: 0x0, reset: 0xFF820000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw
MR30
rw
MR29
rw
MR28
rw
MR27
rw
MR26
rw
MR25
rw
MR24
rw
MR23
rw
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Interrupt Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Interrupt Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Interrupt Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Interrupt Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Interrupt Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Interrupt Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Interrupt Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Interrupt Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Interrupt Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Interrupt Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Interrupt Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Interrupt Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Interrupt Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Interrupt Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Interrupt Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Interrupt Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Interrupt Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Interrupt Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Interrupt Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Interrupt Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Interrupt Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Interrupt Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Interrupt Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Interrupt Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Interrupt Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Interrupt Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Interrupt Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Interrupt Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Interrupt Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Interrupt Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Interrupt Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Interrupt Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR1

Event mask register

Offset: 0x4, reset: 0x00000000, access: read-write

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR31
rw
MR30
rw
MR29
rw
MR28
rw
MR27
rw
MR26
rw
MR25
rw
MR24
rw
MR23
rw
MR22
rw
MR21
rw
MR20
rw
MR19
rw
MR18
rw
MR17
rw
MR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15
rw
MR14
rw
MR13
rw
MR12
rw
MR11
rw
MR10
rw
MR9
rw
MR8
rw
MR7
rw
MR6
rw
MR5
rw
MR4
rw
MR3
rw
MR2
rw
MR1
rw
MR0
rw
Toggle Fields.

MR0

Bit 0: Event Mask on line 0.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR1

Bit 1: Event Mask on line 1.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR2

Bit 2: Event Mask on line 2.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR3

Bit 3: Event Mask on line 3.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR4

Bit 4: Event Mask on line 4.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR5

Bit 5: Event Mask on line 5.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR6

Bit 6: Event Mask on line 6.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR7

Bit 7: Event Mask on line 7.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR8

Bit 8: Event Mask on line 8.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR9

Bit 9: Event Mask on line 9.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR10

Bit 10: Event Mask on line 10.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR11

Bit 11: Event Mask on line 11.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR12

Bit 12: Event Mask on line 12.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR13

Bit 13: Event Mask on line 13.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR14

Bit 14: Event Mask on line 14.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR15

Bit 15: Event Mask on line 15.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR16

Bit 16: Event Mask on line 16.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR17

Bit 17: Event Mask on line 17.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR18

Bit 18: Event Mask on line 18.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR19

Bit 19: Event Mask on line 19.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR20

Bit 20: Event Mask on line 20.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR21

Bit 21: Event Mask on line 21.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR22

Bit 22: Event Mask on line 22.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR23

Bit 23: Event Mask on line 23.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR24

Bit 24: Event Mask on line 24.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR25

Bit 25: Event Mask on line 25.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR26

Bit 26: Event Mask on line 26.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR27

Bit 27: Event Mask on line 27.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR28

Bit 28: Event Mask on line 28.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR29

Bit 29: Event Mask on line 29.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR30

Bit 30: Event Mask on line 30.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR31

Bit 31: Event Mask on line 31.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR1

Rising Trigger selection register

Offset: 0x8, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Rising trigger event configuration of line 0.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR1

Bit 1: Rising trigger event configuration of line 1.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR2

Bit 2: Rising trigger event configuration of line 2.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR3

Bit 3: Rising trigger event configuration of line 3.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR4

Bit 4: Rising trigger event configuration of line 4.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR5

Bit 5: Rising trigger event configuration of line 5.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR6

Bit 6: Rising trigger event configuration of line 6.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR7

Bit 7: Rising trigger event configuration of line 7.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR8

Bit 8: Rising trigger event configuration of line 8.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR9

Bit 9: Rising trigger event configuration of line 9.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR10

Bit 10: Rising trigger event configuration of line 10.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR11

Bit 11: Rising trigger event configuration of line 11.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR12

Bit 12: Rising trigger event configuration of line 12.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR13

Bit 13: Rising trigger event configuration of line 13.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR14

Bit 14: Rising trigger event configuration of line 14.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR15

Bit 15: Rising trigger event configuration of line 15.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR16

Bit 16: Rising trigger event configuration of line 16.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR18

Bit 18: Rising trigger event configuration of line 18.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR19

Bit 19: Rising trigger event configuration of line 19.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR20

Bit 20: Rising trigger event configuration of line 20.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR21

Bit 21: Rising trigger event configuration of line 21.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

TR22

Bit 22: Rising trigger event configuration of line 22.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR1

Falling Trigger selection register

Offset: 0xC, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TR22
rw
TR21
rw
TR20
rw
TR19
rw
TR18
rw
TR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR15
rw
TR14
rw
TR13
rw
TR12
rw
TR11
rw
TR10
rw
TR9
rw
TR8
rw
TR7
rw
TR6
rw
TR5
rw
TR4
rw
TR3
rw
TR2
rw
TR1
rw
TR0
rw
Toggle Fields.

TR0

Bit 0: Falling trigger event configuration of line 0.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR1

Bit 1: Falling trigger event configuration of line 1.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR2

Bit 2: Falling trigger event configuration of line 2.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR3

Bit 3: Falling trigger event configuration of line 3.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR4

Bit 4: Falling trigger event configuration of line 4.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR5

Bit 5: Falling trigger event configuration of line 5.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR6

Bit 6: Falling trigger event configuration of line 6.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR7

Bit 7: Falling trigger event configuration of line 7.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR8

Bit 8: Falling trigger event configuration of line 8.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR9

Bit 9: Falling trigger event configuration of line 9.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR10

Bit 10: Falling trigger event configuration of line 10.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR11

Bit 11: Falling trigger event configuration of line 11.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR12

Bit 12: Falling trigger event configuration of line 12.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR13

Bit 13: Falling trigger event configuration of line 13.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR14

Bit 14: Falling trigger event configuration of line 14.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR15

Bit 15: Falling trigger event configuration of line 15.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR16

Bit 16: Falling trigger event configuration of line 16.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR18

Bit 18: Falling trigger event configuration of line 18.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR19

Bit 19: Falling trigger event configuration of line 19.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR20

Bit 20: Falling trigger event configuration of line 20.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR21

Bit 21: Falling trigger event configuration of line 21.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

TR22

Bit 22: Falling trigger event configuration of line 22.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER1

Software interrupt event register

Offset: 0x10, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWIER22
rw
SWIER21
rw
SWIER20
rw
SWIER19
rw
SWIER18
rw
SWIER16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWIER15
rw
SWIER14
rw
SWIER13
rw
SWIER12
rw
SWIER11
rw
SWIER10
rw
SWIER9
rw
SWIER8
rw
SWIER7
rw
SWIER6
rw
SWIER5
rw
SWIER4
rw
SWIER3
rw
SWIER2
rw
SWIER1
rw
SWIER0
rw
Toggle Fields.

SWIER0

Bit 0: Software Interrupt on line 0.

Allowed values:
1: Pend: Generates an interrupt request

SWIER1

Bit 1: Software Interrupt on line 1.

Allowed values:
1: Pend: Generates an interrupt request

SWIER2

Bit 2: Software Interrupt on line 2.

Allowed values:
1: Pend: Generates an interrupt request

SWIER3

Bit 3: Software Interrupt on line 3.

Allowed values:
1: Pend: Generates an interrupt request

SWIER4

Bit 4: Software Interrupt on line 4.

Allowed values:
1: Pend: Generates an interrupt request

SWIER5

Bit 5: Software Interrupt on line 5.

Allowed values:
1: Pend: Generates an interrupt request

SWIER6

Bit 6: Software Interrupt on line 6.

Allowed values:
1: Pend: Generates an interrupt request

SWIER7

Bit 7: Software Interrupt on line 7.

Allowed values:
1: Pend: Generates an interrupt request

SWIER8

Bit 8: Software Interrupt on line 8.

Allowed values:
1: Pend: Generates an interrupt request

SWIER9

Bit 9: Software Interrupt on line 9.

Allowed values:
1: Pend: Generates an interrupt request

SWIER10

Bit 10: Software Interrupt on line 10.

Allowed values:
1: Pend: Generates an interrupt request

SWIER11

Bit 11: Software Interrupt on line 11.

Allowed values:
1: Pend: Generates an interrupt request

SWIER12

Bit 12: Software Interrupt on line 12.

Allowed values:
1: Pend: Generates an interrupt request

SWIER13

Bit 13: Software Interrupt on line 13.

Allowed values:
1: Pend: Generates an interrupt request

SWIER14

Bit 14: Software Interrupt on line 14.

Allowed values:
1: Pend: Generates an interrupt request

SWIER15

Bit 15: Software Interrupt on line 15.

Allowed values:
1: Pend: Generates an interrupt request

SWIER16

Bit 16: Software Interrupt on line 16.

Allowed values:
1: Pend: Generates an interrupt request

SWIER18

Bit 18: Software Interrupt on line 18.

Allowed values:
1: Pend: Generates an interrupt request

SWIER19

Bit 19: Software Interrupt on line 19.

Allowed values:
1: Pend: Generates an interrupt request

SWIER20

Bit 20: Software Interrupt on line 20.

Allowed values:
1: Pend: Generates an interrupt request

SWIER21

Bit 21: Software Interrupt on line 21.

Allowed values:
1: Pend: Generates an interrupt request

SWIER22

Bit 22: Software Interrupt on line 22.

Allowed values:
1: Pend: Generates an interrupt request

PR1

Pending register

Offset: 0x14, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR22
rw
PR21
rw
PR20
rw
PR19
rw
PR18
rw
PR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR15
rw
PR14
rw
PR13
rw
PR12
rw
PR11
rw
PR10
rw
PR9
rw
PR8
rw
PR7
rw
PR6
rw
PR5
rw
PR4
rw
PR3
rw
PR2
rw
PR1
rw
PR0
rw
Toggle Fields.

PR0

Bit 0: Pending bit 0.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR1

Bit 1: Pending bit 1.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR2

Bit 2: Pending bit 2.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR3

Bit 3: Pending bit 3.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR4

Bit 4: Pending bit 4.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR5

Bit 5: Pending bit 5.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR6

Bit 6: Pending bit 6.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR7

Bit 7: Pending bit 7.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR8

Bit 8: Pending bit 8.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR9

Bit 9: Pending bit 9.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR10

Bit 10: Pending bit 10.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR11

Bit 11: Pending bit 11.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR12

Bit 12: Pending bit 12.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR13

Bit 13: Pending bit 13.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR14

Bit 14: Pending bit 14.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR15

Bit 15: Pending bit 15.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR16

Bit 16: Pending bit 16.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR18

Bit 18: Pending bit 18.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR19

Bit 19: Pending bit 19.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR20

Bit 20: Pending bit 20.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR21

Bit 21: Pending bit 21.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PR22

Bit 22: Pending bit 22.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

IMR2

Interrupt mask register

Offset: 0x20, reset: 0xFFFFFF87, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR39
rw
MR38
rw
MR37
rw
MR36
rw
MR35
rw
MR34
rw
MR33
rw
MR32
rw
Toggle Fields.

MR32

Bit 0: Interrupt Mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Interrupt Mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Interrupt Mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Interrupt Mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR36

Bit 4: Interrupt Mask on external/internal line 36.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR37

Bit 5: Interrupt Mask on external/internal line 37.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR38

Bit 6: Interrupt Mask on external/internal line 38.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR39

Bit 7: Interrupt Mask on external/internal line 39.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

EMR2

Event mask register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR39
rw
MR38
rw
MR37
rw
MR36
rw
MR35
rw
MR34
rw
MR33
rw
MR32
rw
Toggle Fields.

MR32

Bit 0: Event mask on external/internal line 32.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR33

Bit 1: Event mask on external/internal line 33.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR34

Bit 2: Event mask on external/internal line 34.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR35

Bit 3: Event mask on external/internal line 35.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR36

Bit 4: Event mask on external/internal line 36.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR37

Bit 5: Event mask on external/internal line 37.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR38

Bit 6: Event mask on external/internal line 38.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

MR39

Bit 7: Event mask on external/internal line 39.

Allowed values:
0: Masked: Interrupt request line is masked
1: Unmasked: Interrupt request line is unmasked

RTSR2

Rising Trigger selection register

Offset: 0x28, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw
RT37
rw
RT36
rw
RT35
rw
Toggle Fields.

RT35

Bit 3: Rising trigger event configuration bit of line 35.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT36

Bit 4: Rising trigger event configuration bit of line 36.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT37

Bit 5: Rising trigger event configuration bit of line 37.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

RT38

Bit 6: Rising trigger event configuration bit of line 38.

Allowed values:
0: Disabled: Rising edge trigger is disabled
1: Enabled: Rising edge trigger is enabled

FTSR2

Falling Trigger selection register

Offset: 0x2C, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw
FT37
rw
FT36
rw
FT35
rw
Toggle Fields.

FT35

Bit 3: Falling trigger event configuration bit of line 35.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT36

Bit 4: Falling trigger event configuration bit of line 36.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT37

Bit 5: Falling trigger event configuration bit of line 37.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

FT38

Bit 6: Falling trigger event configuration bit of line 38.

Allowed values:
0: Disabled: Falling edge trigger is disabled
1: Enabled: Falling edge trigger is enabled

SWIER2

Software interrupt event register

Offset: 0x30, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw
SWI37
rw
SWI36
rw
SWI35
rw
Toggle Fields.

SWI35

Bit 3: Software interrupt on line 35.

Allowed values:
1: Pend: Generates an interrupt request

SWI36

Bit 4: Software interrupt on line 36.

Allowed values:
1: Pend: Generates an interrupt request

SWI37

Bit 5: Software interrupt on line 37.

Allowed values:
1: Pend: Generates an interrupt request

SWI38

Bit 6: Software interrupt on line 38.

Allowed values:
1: Pend: Generates an interrupt request

PR2

Pending register

Offset: 0x34, reset: 0x00000000, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIF38
rw
PIF37
rw
PIF36
rw
PIF35
rw
Toggle Fields.

PIF35

Bit 3: Pending interrupt flag on line 35.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF36

Bit 4: Pending interrupt flag on line 36.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF37

Bit 5: Pending interrupt flag on line 37.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

PIF38

Bit 6: Pending interrupt flag on line 38.

Allowed values:
0: NotPending: No trigger request occurred
1: Pending: Selected trigger request occurred

FIREWALL

0x40011C00: Firewall

0/9 fields covered. Toggle Registers.

CSSA

Code segment start address

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle Fields.

ADD

Bits 8-23: code segment start address.

CSL

Code segment length

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle Fields.

LENG

Bits 8-21: code segment length.

NVDSSA

Non-volatile data segment start address

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle Fields.

ADD

Bits 8-23: Non-volatile data segment start address.

NVDSL

Non-volatile data segment length

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LENG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle Fields.

LENG

Bits 8-21: Non-volatile data segment length.

VDSSA

Volatile data segment start address

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADD
rw
Toggle Fields.

ADD

Bits 6-15: Volatile data segment start address.

VDSL

Volatile data segment length

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LENG
rw
Toggle Fields.

LENG

Bits 6-15: Non-volatile data segment length.

CR

Configuration register

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDE
rw
VDS
rw
FPA
rw
Toggle Fields.

FPA

Bit 0: Firewall pre alarm.

VDS

Bit 1: Volatile data shared.

VDE

Bit 2: Volatile data execution.

FLASH

0x40022000: Flash

4/72 fields covered. Toggle Registers.

ACR

Access control register

Offset: 0x0, reset: 0x00000600, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP_PD
rw
RUN_PD
rw
DCRST
rw
ICRST
rw
DCEN
rw
ICEN
rw
PRFTEN
rw
LATENCY
rw
Toggle Fields.

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

PDKEYR

Power down key register

Offset: 0x4, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle Fields.

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

KEYR

Flash key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYR
w
Toggle Fields.

KEYR

Bits 0-31: KEYR.

OPTKEYR

Option byte key register

Offset: 0xC, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle Fields.

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw
RDERR
rw
FASTERR
rw
MISERR
rw
PGSERR
rw
SIZERR
rw
PGAERR
rw
WRPERR
rw
PROGERR
rw
OPERR
rw
EOP
rw
Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option validity error.

BSY

Bit 16: Busy.

CR

Flash control register

Offset: 0x14, reset: 0xC0000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
OPTLOCK
rw
OBL_LAUNCH
rw
RDERRIE
rw
ERRIE
rw
EOPIE
rw
FSTPG
rw
OPTSTRT
rw
START
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MER2
rw
BKER
rw
PNB
rw
MER1
rw
PER
rw
PG
rw
Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER1

Bit 2: Bank 1 Mass erase.

PNB

Bits 3-10: Page number.

BKER

Bit 11: Bank erase.

MER2

Bit 15: Bank 2 Mass erase.

START

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, reset: 0x00000000, access: Unspecified

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw
ECCC
rw
ECCIE
rw
SYSF_ECC
r
BK_ECC
r
ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle Fields.

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 19: ECC fail bank.

SYSF_ECC

Bit 20: System Flash ECC fail.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, reset: 0xF0000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
nBOOT0
rw
nSWBOOT0
rw
SRAM2_RST
rw
SRAM2_PE
rw
nBOOT1
rw
DUALBANK
rw
BFB2
rw
WWDG_SW
rw
IWDG_STDBY
rw
IWDG_STOP
rw
IDWG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_STDBY
rw
nRST_STOP
rw
BOR_LEV
rw
RDP
rw
Toggle Fields.

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

IDWG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

BFB2

Bit 20: Dual-bank boot.

DUALBANK

Bit 21: Dual-Bank on 512 KB or 256 KB Flash memory devices.

nBOOT1

Bit 23: Boot configuration.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: Software BOOT0.

nBOOT0

Bit 27: nBOOT0 option bit.

PCROP1SR

Flash Bank 1 PCROP Start address register

Offset: 0x24, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_STRT
rw
Toggle Fields.

PCROP1_STRT

Bits 0-15: Bank 1 PCROP area start offset.

PCROP1ER

Flash Bank 1 PCROP End address register

Offset: 0x28, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCROP_RDP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1_END
rw
Toggle Fields.

PCROP1_END

Bits 0-15: Bank 1 PCROP area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x2C, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_STRT
rw
Toggle Fields.

WRP1A_STRT

Bits 0-7: Bank 1 WRP first area tart offset.

WRP1A_END

Bits 16-23: Bank 1 WRP first area A end offset.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x30, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_STRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_END
rw
Toggle Fields.

WRP1B_END

Bits 0-7: Bank 1 WRP second area B start offset.

WRP1B_STRT

Bits 16-23: Bank 1 WRP second area B end offset.

PCROP2SR

Flash Bank 2 PCROP Start address register

Offset: 0x44, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_STRT
rw
Toggle Fields.

PCROP2_STRT

Bits 0-15: Bank 2 PCROP area start offset.

PCROP2ER

Flash Bank 2 PCROP End address register

Offset: 0x48, reset: 0xFFFF0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2_END
rw
Toggle Fields.

PCROP2_END

Bits 0-15: Bank 2 PCROP area end offset.

WRP2AR

Flash Bank 2 WRP area A address register

Offset: 0x4C, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_STRT
rw
Toggle Fields.

WRP2A_STRT

Bits 0-7: Bank 2 WRP first area A start offset.

WRP2A_END

Bits 16-23: Bank 2 WRP first area A end offset.

WRP2BR

Flash Bank 2 WRP area B address register

Offset: 0x50, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_END
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_STRT
rw
Toggle Fields.

WRP2B_STRT

Bits 0-7: Bank 2 WRP second area B start offset.

WRP2B_END

Bits 16-23: Bank 2 WRP second area B end offset.

FPU

0xE000EF34: Floting point unit

0/24 fields covered. Toggle Registers.

FPCCR

Floating-point context control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ASPEN
rw
LSPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONRDY
rw
BFRDY
rw
MMRDY
rw
HFRDY
rw
THREAD
rw
USER
rw
LSPACT
rw
Toggle Fields.

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
N
rw
Z
rw
C
rw
V
rw
AHP
rw
DN
rw
FZ
rw
RMode
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDC
rw
IXC
rw
UFC
rw
OFC
rw
DZC
rw
IOC
rw
Toggle Fields.

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xE000ED88: Floating point unit CPACR

0/1 fields covered. Toggle Registers.

CPACR

Coprocessor access control register

Offset: 0x0, reset: 0x0000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

CP

Bits 20-23: CP.

GPIOA

0x48000000: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xA8000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOB

0x48000400: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000280, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOC

0x48000800: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOD

0x48000C00: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOE

0x48001000: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

GPIOH

0x48001C00: General-purpose I/Os

161/161 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw
MODER14
rw
MODER13
rw
MODER12
rw
MODER11
rw
MODER10
rw
MODER9
rw
MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw
MODER6
rw
MODER5
rw
MODER4
rw
MODER3
rw
MODER2
rw
MODER1
rw
MODER0
rw
Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Input: Input mode (reset state)
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw
OT14
rw
OT13
rw
OT12
rw
OT11
rw
OT10
rw
OT9
rw
OT8
rw
OT7
rw
OT6
rw
OT5
rw
OT4
rw
OT3
rw
OT2
rw
OT1
rw
OT0
rw
Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT1

Bit 1: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT2

Bit 2: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT3

Bit 3: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT4

Bit 4: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT5

Bit 5: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT6

Bit 6: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT7

Bit 7: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT8

Bit 8: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT9

Bit 9: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT10

Bit 10: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT11

Bit 11: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT12

Bit 12: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT13

Bit 13: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT14

Bit 14: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT15

Bit 15: Port x configuration bits (y = 0..15).

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw
OSPEEDR14
rw
OSPEEDR13
rw
OSPEEDR12
rw
OSPEEDR11
rw
OSPEEDR10
rw
OSPEEDR9
rw
OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw
OSPEEDR6
rw
OSPEEDR5
rw
OSPEEDR4
rw
OSPEEDR3
rw
OSPEEDR2
rw
OSPEEDR1
rw
OSPEEDR0
rw
Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw
PUPDR14
rw
PUPDR13
rw
PUPDR12
rw
PUPDR11
rw
PUPDR10
rw
PUPDR9
rw
PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw
PUPDR6
rw
PUPDR5
rw
PUPDR4
rw
PUPDR3
rw
PUPDR2
rw
PUPDR1
rw
PUPDR0
rw
Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r
IDR14
r
IDR13
r
IDR12
r
IDR11
r
IDR10
r
IDR9
r
IDR8
r
IDR7
r
IDR6
r
IDR5
r
IDR4
r
IDR3
r
IDR2
r
IDR1
r
IDR0
r
Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR1

Bit 1: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR2

Bit 2: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR3

Bit 3: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR4

Bit 4: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR5

Bit 5: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR6

Bit 6: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR7

Bit 7: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR8

Bit 8: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR9

Bit 9: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR10

Bit 10: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR11

Bit 11: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR12

Bit 12: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR13

Bit 13: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR14

Bit 14: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

IDR15

Bit 15: Port input data (y = 0..15).

Allowed values:
1: High: Input is logic high
0: Low: Input is logic low

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw
ODR14
rw
ODR13
rw
ODR12
rw
ODR11
rw
ODR10
rw
ODR9
rw
ODR8
rw
ODR7
rw
ODR6
rw
ODR5
rw
ODR4
rw
ODR3
rw
ODR2
rw
ODR1
rw
ODR0
rw
Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR1

Bit 1: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR2

Bit 2: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR3

Bit 3: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR4

Bit 4: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR5

Bit 5: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR6

Bit 6: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR7

Bit 7: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR8

Bit 8: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR9

Bit 9: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR10

Bit 10: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR11

Bit 11: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR12

Bit 12: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR13

Bit 13: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR14

Bit 14: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

ODR15

Bit 15: Port output data (y = 0..15).

Allowed values:
1: High: Set output to logic high
0: Low: Set output to logic low

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w
BR14
w
BR13
w
BR12
w
BR11
w
BR10
w
BR9
w
BR8
w
BR7
w
BR6
w
BR5
w
BR4
w
BR3
w
BR2
w
BR1
w
BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w
BS14
w
BS13
w
BS12
w
BS11
w
BS10
w
BS9
w
BS8
w
BS7
w
BS6
w
BS5
w
BS4
w
BS3
w
BS2
w
BS1
w
BS0
w
Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS1

Bit 1: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS2

Bit 2: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS3

Bit 3: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS4

Bit 4: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS5

Bit 5: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS6

Bit 6: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS7

Bit 7: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS8

Bit 8: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS9

Bit 9: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS10

Bit 10: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS11

Bit 11: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS12

Bit 12: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS13

Bit 13: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS14

Bit 14: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BS15

Bit 15: Port x set bit y (y= 0..15).

Allowed values:
1: Set: Sets the corresponding ODRx bit

BR0

Bit 16: Port x set bit y (y= 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR1

Bit 17: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR2

Bit 18: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR3

Bit 19: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR4

Bit 20: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR5

Bit 21: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR6

Bit 22: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR7

Bit 23: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR8

Bit 24: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR9

Bit 25: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR10

Bit 26: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR11

Bit 27: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR12

Bit 28: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR13

Bit 29: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR14

Bit 30: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

BR15

Bit 31: Port x reset bit y (y = 0..15).

Allowed values:
1: Reset: Resets the corresponding ODRx bit

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw
LCK14
rw
LCK13
rw
LCK12
rw
LCK11
rw
LCK10
rw
LCK9
rw
LCK8
rw
LCK7
rw
LCK6
rw
LCK5
rw
LCK4
rw
LCK3
rw
LCK2
rw
LCK1
rw
LCK0
rw
Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK1

Bit 1: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK2

Bit 2: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK3

Bit 3: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK4

Bit 4: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK5

Bit 5: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK6

Bit 6: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK7

Bit 7: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK8

Bit 8: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK9

Bit 9: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK10

Bit 10: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK11

Bit 11: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK12

Bit 12: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK13

Bit 13: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK14

Bit 14: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK15

Bit 15: Port x lock bit y (y= 0..15).

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL7
rw
AFRL6
rw
AFRL5
rw
AFRL4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL3
rw
AFRL2
rw
AFRL1
rw
AFRL0
rw
Toggle Fields.

AFRL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH15
rw
AFRH14
rw
AFRH13
rw
AFRH12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH11
rw
AFRH10
rw
AFRH9
rw
AFRH8
rw
Toggle Fields.

AFRH8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

I2C1

0x40005400: Inter-integrated circuit

76/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0-1023

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0-255

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

Allowed values: 0-1023

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

Allowed values: 0-127

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0-255

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0-255

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0-15

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0-15

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0-15

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0-4095

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0-4095

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0-127

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0-255

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0-255

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0-255

I2C2

0x40005800: Inter-integrated circuit

76/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0-1023

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0-255

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

Allowed values: 0-1023

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

Allowed values: 0-127

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0-255

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0-255

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0-15

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0-15

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0-15

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0-4095

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0-4095

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0-127

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0-255

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0-255

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0-255

I2C3

0x40005C00: Inter-integrated circuit

76/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0-1023

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0-255

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

Allowed values: 0-1023

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

Allowed values: 0-127

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0-255

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0-255

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0-15

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0-15

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0-15

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0-4095

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0-4095

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0-127

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0-255

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0-255

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0-255

I2C4

0x40008400: Inter-integrated circuit

76/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle Fields.

PE

Bit 0: Peripheral enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

TXIE

Bit 1: TX Interrupt enable.

Allowed values:
0: Disabled: Transmit (TXIS) interrupt disabled
1: Enabled: Transmit (TXIS) interrupt enabled

RXIE

Bit 2: RX Interrupt enable.

Allowed values:
0: Disabled: Receive (RXNE) interrupt disabled
1: Enabled: Receive (RXNE) interrupt enabled

ADDRIE

Bit 3: Address match interrupt enable (slave only).

Allowed values:
0: Disabled: Address match (ADDR) interrupts disabled
1: Enabled: Address match (ADDR) interrupts enabled

NACKIE

Bit 4: Not acknowledge received interrupt enable.

Allowed values:
0: Disabled: Not acknowledge (NACKF) received interrupts disabled
1: Enabled: Not acknowledge (NACKF) received interrupts enabled

STOPIE

Bit 5: STOP detection Interrupt enable.

Allowed values:
0: Disabled: Stop detection (STOPF) interrupt disabled
1: Enabled: Stop detection (STOPF) interrupt enabled

TCIE

Bit 6: Transfer Complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

ERRIE

Bit 7: Error interrupts enable.

Allowed values:
0: Disabled: Error detection interrupts disabled
1: Enabled: Error detection interrupts enabled

DNF

Bits 8-11: Digital noise filter.

Allowed values:
0: NoFilter: Digital filter disabled
1: Filter1: Digital filter enabled and filtering capability up to 1 tI2CCLK
2: Filter2: Digital filter enabled and filtering capability up to 2 tI2CCLK
3: Filter3: Digital filter enabled and filtering capability up to 3 tI2CCLK
4: Filter4: Digital filter enabled and filtering capability up to 4 tI2CCLK
5: Filter5: Digital filter enabled and filtering capability up to 5 tI2CCLK
6: Filter6: Digital filter enabled and filtering capability up to 6 tI2CCLK
7: Filter7: Digital filter enabled and filtering capability up to 7 tI2CCLK
8: Filter8: Digital filter enabled and filtering capability up to 8 tI2CCLK
9: Filter9: Digital filter enabled and filtering capability up to 9 tI2CCLK
10: Filter10: Digital filter enabled and filtering capability up to 10 tI2CCLK
11: Filter11: Digital filter enabled and filtering capability up to 11 tI2CCLK
12: Filter12: Digital filter enabled and filtering capability up to 12 tI2CCLK
13: Filter13: Digital filter enabled and filtering capability up to 13 tI2CCLK
14: Filter14: Digital filter enabled and filtering capability up to 14 tI2CCLK
15: Filter15: Digital filter enabled and filtering capability up to 15 tI2CCLK

ANFOFF

Bit 12: Analog noise filter OFF.

Allowed values:
0: Enabled: Analog noise filter enabled
1: Disabled: Analog noise filter disabled

TXDMAEN

Bit 14: DMA transmission requests enable.

Allowed values:
0: Disabled: DMA mode disabled for transmission
1: Enabled: DMA mode enabled for transmission

RXDMAEN

Bit 15: DMA reception requests enable.

Allowed values:
0: Disabled: DMA mode disabled for reception
1: Enabled: DMA mode enabled for reception

SBC

Bit 16: Slave byte control.

Allowed values:
0: Disabled: Slave byte control disabled
1: Enabled: Slave byte control enabled

NOSTRETCH

Bit 17: Clock stretching disable.

Allowed values:
0: Enabled: Clock stretching enabled
1: Disabled: Clock stretching disabled

WUPEN

Bit 18: Wakeup from STOP enable.

Allowed values:
0: Disabled: Wakeup from Stop mode disabled
1: Enabled: Wakeup from Stop mode enabled

GCEN

Bit 19: General call enable.

Allowed values:
0: Disabled: General call disabled. Address 0b00000000 is NACKed
1: Enabled: General call enabled. Address 0b00000000 is ACKed

SMBHEN

Bit 20: SMBus Host address enable.

Allowed values:
0: Disabled: Host address disabled. Address 0b0001000x is NACKed
1: Enabled: Host address enabled. Address 0b0001000x is ACKed

SMBDEN

Bit 21: SMBus Device Default address enable.

Allowed values:
0: Disabled: Device default address disabled. Address 0b1100001x is NACKed
1: Enabled: Device default address enabled. Address 0b1100001x is ACKed

ALERTEN

Bit 22: SMBUS alert enable.

Allowed values:
0: Disabled: In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported
1: Enabled: In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported

PECEN

Bit 23: PEC enable.

Allowed values:
0: Disabled: PEC calculation disabled
1: Enabled: PEC calculation enabled

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

Allowed values: 0-1023

RD_WRN

Bit 10: Transfer direction (master mode).

Allowed values:
0: Write: Master requests a write transfer
1: Read: Master requests a read transfer

ADD10

Bit 11: 10-bit addressing mode (master mode).

Allowed values:
0: Bit7: The master operates in 7-bit addressing mode
1: Bit10: The master operates in 10-bit addressing mode

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

Allowed values:
0: Complete: The master sends the complete 10 bit slave address read sequence
1: Partial: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction

START

Bit 13: Start generation.

Allowed values:
0: NoStart: No Start generation
1: Start: Restart/Start generation

STOP

Bit 14: Stop generation (master mode).

Allowed values:
0: NoStop: No Stop generation
1: Stop: Stop generation after current byte transfer

NACK

Bit 15: NACK generation (slave mode).

Allowed values:
0: Ack: an ACK is sent after current received byte
1: Nack: a NACK is sent after current received byte

NBYTES

Bits 16-23: Number of bytes.

Allowed values: 0-255

RELOAD

Bit 24: NBYTES reload mode.

Allowed values:
0: Completed: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
1: NotCompleted: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)

AUTOEND

Bit 25: Automatic end mode (master mode).

Allowed values:
0: Software: Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low
1: Automatic: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred

PECBYTE

Bit 26: Packet error checking byte.

Allowed values:
0: NoPec: No PEC transfer
1: Pec: PEC transmission/reception is requested

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle Fields.

OA1

Bits 0-9: Interface address.

Allowed values: 0-1023

OA1MODE

Bit 10: Own Address 1 10-bit mode.

Allowed values:
0: Bit7: Own address 1 is a 7-bit address
1: Bit10: Own address 1 is a 10-bit address

OA1EN

Bit 15: Own Address 1 enable.

Allowed values:
0: Disabled: Own address 1 disabled. The received slave address OA1 is NACKed
1: Enabled: Own address 1 enabled. The received slave address OA1 is ACKed

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle Fields.

OA2

Bits 1-7: Interface address.

Allowed values: 0-127

OA2MSK

Bits 8-10: Own Address 2 masks.

Allowed values:
0: NoMask: No mask
1: Mask1: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
2: Mask2: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
3: Mask3: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
4: Mask4: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
5: Mask5: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
6: Mask6: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
7: Mask7: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged

OA2EN

Bit 15: Own Address 2 enable.

Allowed values:
0: Disabled: Own address 2 disabled. The received slave address OA2 is NACKed
1: Enabled: Own address 2 enabled. The received slave address OA2 is ACKed

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

Allowed values: 0-255

SCLH

Bits 8-15: SCL high period (master mode).

Allowed values: 0-255

SDADEL

Bits 16-19: Data hold time.

Allowed values: 0-15

SCLDEL

Bits 20-23: Data setup time.

Allowed values: 0-15

PRESC

Bits 28-31: Timing prescaler.

Allowed values: 0-15

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

Allowed values: 0-4095

TIDLE

Bit 12: Idle clock timeout detection.

Allowed values:
0: Disabled: TIMEOUTA is used to detect SCL low timeout
1: Enabled: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

TIMOUTEN

Bit 15: Clock timeout enable.

Allowed values:
0: Disabled: SCL timeout detection is disabled
1: Enabled: SCL timeout detection is enabled

TIMEOUTB

Bits 16-27: Bus timeout B.

Allowed values: 0-4095

TEXTEN

Bit 31: Extended clock timeout enable.

Allowed values:
0: Disabled: Extended clock timeout detection is disabled
1: Enabled: Extended clock timeout detection is enabled

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

Allowed values:
0: NotEmpty: TXDR register not empty
1: Empty: TXDR register empty

TXIS

Bit 1: Transmit interrupt status (transmitters).

Allowed values:
0: NotEmpty: The TXDR register is not empty
1: Empty: The TXDR register is empty and the data to be transmitted must be written in the TXDR register

RXNE

Bit 2: Receive data register not empty (receivers).

Allowed values:
0: Empty: The RXDR register is empty
1: NotEmpty: Received data is copied into the RXDR register, and is ready to be read

ADDR

Bit 3: Address matched (slave mode).

Allowed values:
0: NotMatch: Adress mismatched or not received
1: Match: Received slave address matched with one of the enabled slave addresses

NACKF

Bit 4: Not acknowledge received flag.

Allowed values:
0: NoNack: No NACK has been received
1: Nack: NACK has been received

STOPF

Bit 5: Stop detection flag.

Allowed values:
0: NoStop: No Stop condition detected
1: Stop: Stop condition detected

TC

Bit 6: Transfer Complete (master mode).

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

TCR

Bit 7: Transfer Complete Reload.

Allowed values:
0: NotComplete: Transfer is not complete
1: Complete: NBYTES has been transfered

BERR

Bit 8: Bus error.

Allowed values:
0: NoError: No bus error
1: Error: Misplaced Start and Stop condition is detected

ARLO

Bit 9: Arbitration lost.

Allowed values:
0: NotLost: No arbitration lost
1: Lost: Arbitration lost

OVR

Bit 10: Overrun/Underrun (slave mode).

Allowed values:
0: NoOverrun: No overrun/underrun error occurs
1: Overrun: slave mode with NOSTRETCH=1, when an overrun/underrun error occurs

PECERR

Bit 11: PEC Error in reception.

Allowed values:
0: Match: Received PEC does match with PEC register
1: NoMatch: Received PEC does not match with PEC register

TIMEOUT

Bit 12: Timeout or t_low detection flag.

Allowed values:
0: NoTimeout: No timeout occured
1: Timeout: Timeout occured

ALERT

Bit 13: SMBus alert.

Allowed values:
0: NoAlert: SMBA alert is not detected
1: Alert: SMBA alert event is detected on SMBA pin

BUSY

Bit 15: Bus busy.

Allowed values:
0: NotBusy: No communication is in progress on the bus
1: Busy: A communication is in progress on the bus

DIR

Bit 16: Transfer direction (Slave mode).

Allowed values:
0: Write: Write transfer, slave enters receiver mode
1: Read: Read transfer, slave enters transmitter mode

ADDCODE

Bits 17-23: Address match code (Slave mode).

Allowed values: 0-127

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w
TIMOUTCF
w
PECCF
w
OVRCF
w
ARLOCF
w
BERRCF
w
STOPCF
w
NACKCF
w
ADDRCF
w
Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

Allowed values:
1: Clear: Clears the ADDR flag in ISR register

NACKCF

Bit 4: Not Acknowledge flag clear.

Allowed values:
1: Clear: Clears the NACK flag in ISR register

STOPCF

Bit 5: Stop detection flag clear.

Allowed values:
1: Clear: Clears the STOP flag in ISR register

BERRCF

Bit 8: Bus error flag clear.

Allowed values:
1: Clear: Clears the BERR flag in ISR register

ARLOCF

Bit 9: Arbitration lost flag clear.

Allowed values:
1: Clear: Clears the ARLO flag in ISR register

OVRCF

Bit 10: Overrun/Underrun flag clear.

Allowed values:
1: Clear: Clears the OVR flag in ISR register

PECCF

Bit 11: PEC Error flag clear.

Allowed values:
1: Clear: Clears the PEC flag in ISR register

TIMOUTCF

Bit 12: Timeout detection flag clear.

Allowed values:
1: Clear: Clears the TIMOUT flag in ISR register

ALERTCF

Bit 13: Alert flag clear.

Allowed values:
1: Clear: Clears the ALERT flag in ISR register

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

Allowed values: 0-255

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

Allowed values: 0-255

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

Allowed values: 0-255

IWDG

0x40003000: Independent watchdog

7/7 fields covered. Toggle Registers.

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-15: Key value (write only, read 0x0000).

Allowed values:
21845: Enable: Enable access to PR, RLR and WINR registers (0x5555)
43690: Reset: Reset the watchdog value (0xAAAA)
52428: Start: Start the watchdog (0xCCCC)

PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle Fields.

PR

Bits 0-2: Prescaler divider.

Allowed values:
0: DivideBy4: Divider /4
1: DivideBy8: Divider /8
2: DivideBy16: Divider /16
3: DivideBy32: Divider /32
4: DivideBy64: Divider /64
5: DivideBy128: Divider /128
6: DivideBy256: Divider /256
7: DivideBy256bis: Divider /256

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

Allowed values: 0-4095

SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r
RVU
r
PVU
r
Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle Fields.

WIN

Bits 0-11: Watchdog counter window value.

Allowed values: 0-4095

LCD

0x40002400: Liquid crystal display controller

5/279 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUFEN
rw
MUX_SEG
rw
BIAS
rw
DUTY
rw
VSEL
rw
LCDEN
rw
Toggle Fields.

LCDEN

Bit 0: LCD controller enable.

VSEL

Bit 1: Voltage source selection.

DUTY

Bits 2-4: Duty selection.

BIAS

Bits 5-6: Bias selector.

MUX_SEG

Bit 7: Mux segment enable.

BUFEN

Bit 8: Voltage output buffer enable.

FCR

frame control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PS
rw
DIV
rw
BLINK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLINKF
rw
CC
rw
DEAD
rw
PON
rw
UDDIE
rw
SOFIE
rw
HD
rw
Toggle Fields.

HD

Bit 0: High drive enable.

SOFIE

Bit 1: Start of frame interrupt enable.

UDDIE

Bit 3: Update display done interrupt enable.

PON

Bits 4-6: Pulse ON duration.

DEAD

Bits 7-9: Dead time duration.

CC

Bits 10-12: Contrast control.

BLINKF

Bits 13-15: Blink frequency selection.

BLINK

Bits 16-17: Blink mode selection.

DIV

Bits 18-21: DIV clock divider.

PS

Bits 22-25: PS 16-bit prescaler.

SR

status register

Offset: 0x8, reset: 0x00000020, access: Unspecified

5/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FCRSF
r
RDY
r
UDD
r
UDR
w
SOF
r
ENS
r
Toggle Fields.

ENS

Bit 0: ENS.

SOF

Bit 1: Start of frame flag.

UDR

Bit 2: Update display request.

UDD

Bit 3: Update Display Done.

RDY

Bit 4: Ready flag.

FCRSF

Bit 5: LCD Frame Control Register Synchronization flag.

CLR

clear register

Offset: 0xC, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDDC
w
SOFC
w
Toggle Fields.

SOFC

Bit 1: Start of frame flag clear.

UDDC

Bit 3: Update display done clear.

RAM_COM0

display memory

Offset: 0x14, reset: 0x00000000, access: read-write

0/31 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

RAM_COM1

display memory

Offset: 0x1C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM2

display memory

Offset: 0x24, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM3

display memory

Offset: 0x2C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM4

display memory

Offset: 0x34, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM5

display memory

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM6

display memory

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM7

display memory

Offset: 0x4C, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S31
rw
S30
rw
S29
rw
S28
rw
S27
rw
S26
rw
S25
rw
S24
rw
S23
rw
S22
rw
S21
rw
S20
rw
S19
rw
S18
rw
S17
rw
S16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S15
rw
S14
rw
S13
rw
S12
rw
S11
rw
S10
rw
S09
rw
S08
rw
S07
rw
S06
rw
S05
rw
S04
rw
S03
rw
S02
rw
S01
rw
S00
rw
Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

LPTIM1

0x40007C00: Low power timer

8/40 fields covered. Toggle Registers.

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPTIM2

0x40009400: Low power timer

8/40 fields covered. Toggle Registers.

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w
UPCF
w
ARROKCF
w
CMPOKCF
w
EXTTRIGCF
w
ARRMCF
w
CMPMCF
w
Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle Fields.

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle Fields.

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-15: Counter value.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

72/72 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0-31

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
STOP
rw
CLKEN
rw
ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw
WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
HDSEL
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-19: BRR.

Allowed values: 0-1048575

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFRQ
w
MMRQ
w
SBKRQ
w
Toggle Fields.

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r
CTSIF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w
TCCF
w
IDLECF
w
ORECF
w
NCF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

Allowed values: 0-255

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

Allowed values: 0-255

MPU

0xE000ED90: Memory protection unit

6/19 fields covered. Toggle Registers.

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IREGION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DREGION
r
SEPARATE
r
Toggle Fields.

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIVDEFENA
r
HFNMIENA
r
ENABLE
r
Toggle Fields.

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGION
rw
Toggle Fields.

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
rw
VALID
rw
REGION
rw
Toggle Fields.

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XN
rw
AP
rw
TEX
rw
S
rw
C
rw
B
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRD
rw
SIZE
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

3/99 fields covered. Toggle Registers.

ISER0

Interrupt Set-Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw
IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw
IPR_N0
rw
Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xE000EF00: Nested vectored interrupt controller

0/1 fields covered. Toggle Registers.

STIR

Software trigger interrupt register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTID
rw
Toggle Fields.

INTID

Bits 0-8: Software generated interrupt ID.

OPAMP

0x40007800: Operational amplifiers

0/29 fields covered. Toggle Registers.

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle Fields.

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enabled.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: allows to switch from AOP offset trimmed values to AOP offset.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle Fields.

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-power mode

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle Fields.

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CSR

OPAMP2 control/status register

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle Fields.

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: Inverting input selection.

VP_SEL

Bit 10: Non inverted input selection.

CALON

Bit 12: Calibration mode enabled.

CALSEL

Bit 13: Calibration selection.

USERTRIM

Bit 14: allows to switch from AOP offset trimmed values to AOP offset.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle Fields.

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle Fields.

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

PWR

0x40007000: Power control

15/276 fields covered. Toggle Registers.

CR1

Power control register 1

Offset: 0x0, reset: 0x00000200, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw
VOS
rw
DBP
rw
LPMS
rw
Toggle Fields.

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw
IOSV
rw
PVME4
rw
PVME3
rw
PVME2
rw
PVME1
rw
PLS
rw
PVDE
rw
Toggle Fields.

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, reset: 0X00008000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWF
rw
APC
rw
RRS
rw
EWUP5
rw
EWUP4
rw
EWUP3
rw
EWUP2
rw
EWUP1
rw
Toggle Fields.

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bit 8: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

EWF

Bit 15: Enable internal wakeup line.

CR4

Power control register 4

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBRS
rw
VBE
rw
WP5
rw
WP4
rw
WP3
rw
WP2
rw
WP1
rw
Toggle Fields.

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP3

Bit 2: Wakeup pin WKUP3 polarity.

WP4

Bit 3: Wakeup pin WKUP4 polarity.

WP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SR1

Power status register 1

Offset: 0x10, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUFI
r
CSBF
r
CWUF5
r
CWUF4
r
CWUF3
r
CWUF2
r
CWUF1
r
Toggle Fields.

CWUF1

Bit 0: Wakeup flag 1.

CWUF2

Bit 1: Wakeup flag 2.

CWUF3

Bit 2: Wakeup flag 3.

CWUF4

Bit 3: Wakeup flag 4.

CWUF5

Bit 4: Wakeup flag 5.

CSBF

Bit 8: Standby flag.

WUFI

Bit 15: Wakeup flag internal.

SR2

Power status register 2

Offset: 0x14, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r
PVMO3
r
PVMO2
r
PVMO1
r
PVDO
r
VOSF
r
REGLPF
r
REGLPS
r
Toggle Fields.

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, reset: 0x00000000, access: write-only

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBF
w
WUF5
w
WUF4
w
WUF3
w
WUF2
w
WUF1
w
Toggle Fields.

WUF1

Bit 0: Clear wakeup flag 1.

WUF2

Bit 1: Clear wakeup flag 2.

WUF3

Bit 2: Clear wakeup flag 3.

WUF4

Bit 3: Clear wakeup flag 4.

WUF5

Bit 4: Clear wakeup flag 5.

SBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU1
rw
PU0
rw
Toggle Fields.

PU0

Bit 0: Port H pull-up bit y (y=0..1).

PU1

Bit 1: Port H pull-up bit y (y=0..1).

PDCRH

Power Port H pull-down control register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD1
rw
PD0
rw
Toggle Fields.

PD0

Bit 0: Port H pull-down bit y (y=0..1).

PD1

Bit 1: Port H pull-down bit y (y=0..1).

QUADSPI

0xA0001000: QuadSPI interface

7/50 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESCALER
rw
PMM
rw
APMS
rw
TOIE
rw
SMIE
rw
FTIE
rw
TCIE
rw
TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw
FSEL
rw
DFM
rw
SSHIFT
rw
TCEN
rw
DMAEN
rw
ABORT
rw
EN
rw
Toggle Fields.

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

SSHIFT

Bit 4: Sample shift.

DFM

Bit 6: Dual-flash mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

PRESCALER

Bits 24-31: Clock prescaler.

DCR

device configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw
CKMODE
rw
Toggle Fields.

CKMODE

Bit 0: Mode 0 / mode 3.

CSHT

Bits 8-10: Chip select high time.

FSIZE

Bits 16-20: FLASH memory size.

SR

status register

Offset: 0x8, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
r
BUSY
r
TOF
r
SMF
r
FTF
r
TCF
r
TEF
r
Toggle Fields.

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: Busy.

FLEVEL

Bits 8-14: FIFO level.

FCR

flag clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
rw
CSMF
rw
CTCF
rw
CTEF
rw
Toggle Fields.

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle Fields.

DL

Bits 0-31: Data length.

CCR

communication configuration register

Offset: 0x14, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDRM
rw
DHHC
rw
SIOO
rw
FMODE
rw
DMODE
rw
DCYC
rw
ABSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABMODE
rw
ADSIZE
rw
ADMODE
rw
IMODE
rw
INSTRUCTION
rw
Toggle Fields.

INSTRUCTION

Bits 0-7: Instruction.

IMODE

Bits 8-9: Instruction mode.

ADMODE

Bits 10-11: Address mode.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 14-15: Alternate bytes mode.

ABSIZE

Bits 16-17: Alternate bytes size.

DCYC

Bits 18-22: Number of dummy cycles.

DMODE

Bits 24-25: Data mode.

FMODE

Bits 26-27: Functional mode.

SIOO

Bit 28: Send instruction only once mode.

DHHC

Bit 30: DDR hold half cycle.

DDRM

Bit 31: Double data rate mode.

AR

address register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle Fields.

ADDRESS

Bits 0-31: Address.

ABR

ABR

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle Fields.

ALTERNATE

Bits 0-31: ALTERNATE.

DR

data register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle Fields.

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle Fields.

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle Fields.

INTERVAL

Bits 0-15: Polling interval.

LPTR

low-power timeout register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle Fields.

TIMEOUT

Bits 0-15: Timeout period.

RCC

0x40021000: Reset and clock control

33/263 fields covered. Toggle Registers.

CR

Clock control register

Offset: 0x0, reset: 0x00000063, access: Unspecified

6/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1RDY
r
PLLSAI1ON
rw
PLLRDY
r
PLLON
rw
CSSON
w
HSEBYP
rw
HSERDY
r
HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw
HSIRDY
r
HSIKERON
rw
HSION
rw
MSIRANGE
rw
MSIRGSEL
w
MSIPLLEN
rw
MSIRDY
r
MSION
rw
Toggle Fields.

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

Allowed values:
0: Range100K: range 0 around 100 kHz
1: Range200K: range 1 around 200 kHz
2: Range400K: range 2 around 400 kHz
3: Range800K: range 3 around 800 kHz
4: Range1M: range 4 around 1 MHz
5: Range2M: range 5 around 2 MHz
6: Range4M: range 6 around 4 MHz
7: Range8M: range 7 around 8 MHz
8: Range16M: range 8 around 16 MHz
9: Range24M: range 9 around 24 MHz
10: Range32M: range 10 around 32 MHz
11: Range48M: range 11 around 48 MHz

HSION

Bit 8: HSI clock enable.

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE crystal oscillator bypass.

CSSON

Bit 19: Clock security system enable.

PLLON

Bit 24: Main PLL enable.

PLLRDY

Bit 25: Main PLL clock ready flag.

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, reset: 0x10000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw
HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw
MSICAL
r
Toggle Fields.

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-28: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, reset: 0x00000000, access: Unspecified

2/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r
MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw
PPRE2
rw
PPRE1
rw
HPRE
rw
SWS
r
SW
rw
Toggle Fields.

SW

Bits 0-1: System clock switch.

SWS

Bits 2-3: System clock switch status.

HPRE

Bits 4-7: AHB prescaler.

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

MCOSEL

Bits 24-26: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLCFGR

PLL configuration register

Offset: 0xC, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw
PLLR
rw
PLLREN
rw
PLLQ
rw
PLLQEN
rw
PLLP
rw
PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw
PLLM
rw
PLLSRC
rw
Toggle Fields.

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-6: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, reset: 0x00001000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw
PLLSAI1R
rw
PLLSAI1REN
rw
PLLSAI1Q
rw
PLLSAI1QEN
rw
PLLSAI1P
rw
PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw
Toggle Fields.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

CIER

Clock interrupt enable register

Offset: 0x18, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYIE
rw
LSECSSIE
rw
PLLSAI1RDYIE
rw
PLLRDYIE
rw
HSERDYIE
rw
HSIRDYIE
rw
MSIRDYIE
rw
LSERDYIE
rw
LSIRDYIE
rw
Toggle Fields.

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1C, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYF
r
LSECSSF
r
CSSF
r
PLLSAI1RDYF
r
PLLRDYF
r
HSERDYF
r
HSIRDYF
r
MSIRDYF
r
LSERDYF
r
LSIRDYF
r
Toggle Fields.

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, reset: 0x00000000, access: write-only

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDYC
w
LSECSSC
w
CSSC
w
PLLSAI1RDYC
w
PLLRDYC
w
HSERDYC
w
HSIRDYC
w
MSIRDYC
w
LSERDYC
w
LSIRDYC
w
Toggle Fields.

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw
FLASHRST
rw
DMA2RST
rw
DMA1RST
rw
Toggle Fields.

DMA1RST

Bit 0: DMA1 reset.

DMA2RST

Bit 1: DMA2 reset.

FLASHRST

Bit 8: Flash memory interface reset.

CRCRST

Bit 11: CRC reset.

TSCRST

Bit 16: Touch Sensing Controller reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNGRST
rw
AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCRST
rw
GPIOHRST
rw
GPIOERST
rw
GPIODRST
rw
GPIOCRST
rw
GPIOBRST
rw
GPIOARST
rw
Toggle Fields.

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIODRST

Bit 3: IO port D reset.

GPIOERST

Bit 4: IO port E reset.

GPIOHRST

Bit 7: IO port H reset.

ADCRST

Bit 13: ADC reset.

AESRST

Bit 16: AES hardware accelerator reset.

RNGRST

Bit 18: Random number generator reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIRST
rw
Toggle Fields.

QSPIRST

Bit 8: Quad SPI memory interface reset.

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw
OPAMPRST
rw
DAC1RST
rw
PWRRST
rw
USBFSRST
rw
CAN1RST
rw
CRSRST
rw
I2C3RST
rw
I2C2RST
rw
I2C1RST
rw
USART4RST
rw
USART3RST
rw
USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw
SPI2RST
rw
LCDRST
rw
TIM7RST
rw
TIM6RST
rw
TIM3RST
rw
TIM2RST
rw
Toggle Fields.

TIM2RST

Bit 0: TIM2 timer reset.

TIM3RST

Bit 1: TIM3 timer reset.

TIM6RST

Bit 4: TIM6 timer reset.

TIM7RST

Bit 5: TIM7 timer reset.

LCDRST

Bit 9: LCD interface reset.

SPI2RST

Bit 14: SPI2 reset.

SPI3RST

Bit 15: SPI3 reset.

USART2RST

Bit 17: USART2 reset.

USART3RST

Bit 18: USART3 reset.

USART4RST

Bit 19: USART4 reset..

I2C1RST

Bit 21: I2C1 reset.

I2C2RST

Bit 22: I2C2 reset.

I2C3RST

Bit 23: I2C3 reset.

CRSRST

Bit 24: CRS reset.

CAN1RST

Bit 25: CAN1 reset.

USBFSRST

Bit 26: USB FS reset.

PWRRST

Bit 28: Power interface reset.

DAC1RST

Bit 29: DAC1 interface reset.

OPAMPRST

Bit 30: OPAMP interface reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2RST
rw
SWPMI1RST
rw
I2C4RST
rw
LPUART1RST
rw
Toggle Fields.

LPUART1RST

Bit 0: Low-power UART 1 reset.

I2C4RST

Bit 1: I2C4 reset.

SWPMI1RST

Bit 2: Single wire protocol reset.

LPTIM2RST

Bit 5: Low-power timer 2 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMRST
rw
SAI1RST
rw
TIM16RST
rw
TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw
SPI1RST
rw
TIM1RST
rw
SDMMCRST
rw
SYSCFGRST
rw
Toggle Fields.

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

SDMMCRST

Bit 10: SDMMC reset.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM15RST

Bit 16: TIM15 timer reset.

TIM16RST

Bit 17: TIM16 timer reset.

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

DFSDMRST

Bit 24: DFSDM filter reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, reset: 0x00000100, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw
FLASHEN
rw
DMA2EN
rw
DMA1EN
rw
Toggle Fields.

DMA1EN

Bit 0: DMA1 clock enable.

DMA2EN

Bit 1: DMA2 clock enable.

FLASHEN

Bit 8: Flash memory interface clock enable.

CRCEN

Bit 12: CRC clock enable.

TSCEN

Bit 16: Touch Sensing Controller clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNGEN
rw
AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCEN
rw
GPIOHEN
rw
GPIOEEN
rw
GPIODEN
rw
GPIOCEN
rw
GPIOBEN
rw
GPIOAEN
rw
Toggle Fields.

GPIOAEN

Bit 0: IO port A clock enable.

GPIOBEN

Bit 1: IO port B clock enable.

GPIOCEN

Bit 2: IO port C clock enable.

GPIODEN

Bit 3: IO port D clock enable.

GPIOEEN

Bit 4: IO port E clock enable.

GPIOHEN

Bit 7: IO port H clock enable.

ADCEN

Bit 13: ADC clock enable.

AESEN

Bit 16: AES accelerator clock enable.

RNGEN

Bit 18: Random Number Generator clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIEN
rw
Toggle Fields.

QSPIEN

Bit 8: QSPIEN.

APB1ENR1

APB1ENR1

Offset: 0x58, reset: 0x00000000, access: read-write

0/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw
OPAMPEN
rw
DAC1EN
rw
PWREN
rw
USBFSEN
rw
CAN1EN
rw
CRSEN
rw
I2C3EN
rw
I2C2EN
rw
I2C1EN
rw
UART4EN
rw
USART3EN
rw
USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3EN
rw
SPI2EN
rw
WWDGEN
rw
RTCAPBEN
rw
LCDEN
rw
TIM7EN
rw
TIM6EN
rw
TIM3EN
rw
TIM2EN
rw
Toggle Fields.

TIM2EN

Bit 0: TIM2 timer clock enable.

TIM3EN

Bit 1: TIM3 timer clock enable.

TIM6EN

Bit 4: TIM6 timer clock enable.

TIM7EN

Bit 5: TIM7 timer clock enable.

LCDEN

Bit 9: LCD clock enable.

RTCAPBEN

Bit 10: RTC APB clock enable.

WWDGEN

Bit 11: Window watchdog clock enable.

SPI2EN

Bit 14: SPI2 clock enable.

SPI3EN

Bit 15: SPI3 clock enable.

USART2EN

Bit 17: USART2 clock enable.

USART3EN

Bit 18: USART3 clock enable.

UART4EN

Bit 19: UART4 clock enable.

I2C1EN

Bit 21: I2C1 clock enable.

I2C2EN

Bit 22: I2C2 clock enable.

I2C3EN

Bit 23: I2C3 clock enable.

CRSEN

Bit 24: CRS clock enable.

CAN1EN

Bit 25: CAN1 clock enable.

USBFSEN

Bit 26: USB FS clock enable.

PWREN

Bit 28: Power interface clock enable.

DAC1EN

Bit 29: DAC1 interface clock enable.

OPAMPEN

Bit 30: OPAMP interface clock enable.

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5C, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2EN
rw
SWPMI1EN
rw
I2C4EN
rw
LPUART1EN
rw
Toggle Fields.

LPUART1EN

Bit 0: Low power UART 1 clock enable.

I2C4EN

Bit 1: I2C4 clock enable.

SWPMI1EN

Bit 2: Single wire protocol clock enable.

LPTIM2EN

Bit 5: LPTIM2EN.

DFSDMEN

Bit 24: DFSDMEN enable.

APB2ENR

APB2ENR

Offset: 0x60, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI1EN
rw
TIM16EN
rw
TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw
SPI1EN
rw
TIM1EN
rw
SDMMCEN
rw
FIREWALLEN
rw
SYSCFGEN
rw
Toggle Fields.

SYSCFGEN

Bit 0: SYSCFG clock enable.

FIREWALLEN

Bit 7: Firewall clock enable.

SDMMCEN

Bit 10: SDMMC clock enable.

TIM1EN

Bit 11: TIM1 timer clock enable.

SPI1EN

Bit 12: SPI1 clock enable.

USART1EN

Bit 14: USART1clock enable.

TIM15EN

Bit 16: TIM15 timer clock enable.

TIM16EN

Bit 17: TIM16 timer clock enable.

SAI1EN

Bit 21: SAI1 clock enable.

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, reset: 0x00011303, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw
SRAM1SMEN
rw
FLASHSMEN
rw
DMA2SMEN
rw
DMA1SMEN
rw
Toggle Fields.

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6C, reset: 0x000532FF, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNGSMEN
rw
AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCFSSMEN
rw
SRAM2SMEN
rw
GPIOHSMEN
rw
GPIOESMEN
rw
GPIODSMEN
rw
GPIOCSMEN
rw
GPIOBSMEN
rw
GPIOASMEN
rw
Toggle Fields.

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, reset: 0x000000101, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPISMEN
rw
Toggle Fields.

QSPISMEN

Bit 8: QSPISMEN.

APB1SMENR1

APB1SMENR1

Offset: 0x78, reset: 0xF2FECA3F, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1SMEN
rw
OPAMPSMEN
rw
DAC1SMEN
rw
PWRSMEN
rw
USBFSSMEN
rw
CAN1SMEN
rw
CRSSMEN
rw
I2C3SMEN
rw
I2C2SMEN
rw
I2C1SMEN
rw
USART2SMEN
rw
USART1SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3SMEN
rw
SPI2SMEN
rw
WWDGSMEN
rw
RTCAPBSMEN
rw
LCDSMEN
rw
TIM7SMEN
rw
TIM6SMEN
rw
TIM2SMEN
rw
Toggle Fields.

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

LCDSMEN

Bit 9: LCD clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 17: USART1 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 18: USART2 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

CAN1SMEN

Bit 25: CAN1 clocks enable during Sleep and Stop modes.

USBFSSMEN

Bit 26: USB FS clock enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7C, reset: 0x000000025, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM2SMEN
rw
SWPMI1SMEN
rw
LPUART1SMEN
rw
Toggle Fields.

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

SWPMI1SMEN

Bit 2: Single wire protocol clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, reset: 0x01677C01, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAI1SMEN
rw
TIM16SMEN
rw
TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw
SPI1SMEN
rw
TIM1SMEN
rw
SDMMCSMEN
rw
SYSCFGSMEN
rw
Toggle Fields.

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

SDMMCSMEN

Bit 10: SDMMC clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

CCIPR

CCIPR

Offset: 0x88, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWPMI1SEL
rw
ADCSEL
rw
CLK48SEL
rw
SAI1SEL
rw
LPTIM2SEL
rw
LPTIM1SEL
rw
I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw
I2C1SEL
rw
LPUART1SEL
rw
USART4SEL
rw
USART3SEL
rw
USART2SEL
rw
USART1SEL
rw
Toggle Fields.

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

USART3SEL

Bits 4-5: USART3 clock source selection.

USART4SEL

Bits 6-7: USART4 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

SAI1SEL

Bits 22-23: SAI1 clock source selection.

CLK48SEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

SWPMI1SEL

Bit 30: SWPMI1 clock source selection.

BDCR

BDCR

Offset: 0x90, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw
LSCOEN
rw
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
RTCSEL
rw
LSECSSD
r
LSECSSON
rw
LSEDRV
rw
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle Fields.

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: SE oscillator drive capability.

LSECSSON

Bit 5: LSECSSON.

LSECSSD

Bit 6: LSECSSD.

RTCSEL

Bits 8-9: RTC clock source selection.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: Backup domain software reset.

LSCOEN

Bit 24: Low speed clock output enable.

LSCOSEL

Bit 25: Low speed clock output selection.

CSR

CSR

Offset: 0x94, reset: 0x0C000600, access: Unspecified

9/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r
WWDGRSTF
r
IWDGRSTF
r
SFTRSTF
r
BORRSTF
r
PINRSTF
r
OBLRSTF
r
FIREWALLRSTF
r
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw
LSIRDY
r
LSION
rw
Toggle Fields.

LSION

Bit 0: LSI oscillator enable.

LSIRDY

Bit 1: LSI oscillator ready.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

FIREWALLRSTF

Bit 24: Firewall reset flag.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

BORRSTF

Bit 27: BOR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRSTF

Bit 31: Low-power reset flag.

CRRCR

Clock recovery RC register

Offset: 0x98, reset: 0x0C000600, access: Unspecified

2/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r
HSI48RDY
r
HSI48ON
rw
Toggle Fields.

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

RNG

0x50060800: Random number generator

4/8 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IE
rw
RNGEN
rw
Toggle Fields.

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

SR

status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle Fields.

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle Fields.

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

20/132 fields covered. Toggle Registers.

TR

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITSE
rw
COE
rw
OSEL
rw
POL
rw
COSEL
rw
BKP
rw
SUB1H
rw
ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw
WUTIE
rw
ALRBIE
rw
ALRAIE
rw
TSE
rw
WUTE
rw
ALRBE
rw
ALRAE
rw
FMT
rw
BYPSHAD
rw
REFCKON
rw
TSEDGE
rw
WUCKSEL
rw
Toggle Fields.

WUCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ITSE

Bit 24: timestamp on internal event enable.

ISR

initialization and status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

6/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
rw
TAMP2F
rw
TAMP1F
rw
TSOVF
rw
TSF
rw
WUTF
rw
ALRBF
rw
ALRAF
rw
INIT
rw
INITF
r
RSF
rw
INITS
r
SHPF
rw
WUTWF
r
ALRBWF
r
ALRAWF
r
Toggle Fields.

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: RTC_TAMP2 detection flag.

TAMP3F

Bit 15: RTC_TAMP3 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

PRER

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle Fields.

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle Fields.

WUT

Bits 0-15: Wakeup auto-reload value bits.

ALRMAR

alarm A register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMBR

alarm B register

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

WPR

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle Fields.

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle Fields.

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
r
HT
r
HU
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
r
MNU
r
ST
r
SU
r
Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
r
MT
r
MU
r
DT
r
DU
r
Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle Fields.

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw
CALW8
rw
CALW16
rw
CALM
rw
Toggle Fields.

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

TAMPCR

tamper configuration register

Offset: 0x40, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3MF
rw
TAMP3NOERASE
rw
TAMP3IE
rw
TAMP2MF
rw
TAMP2NOERASE
rw
TAMP2IE
rw
TAMP1MF
rw
TAMP1NOERASE
rw
TAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw
TAMPPRCH
rw
TAMPFLT
rw
TAMPFREQ
rw
TAMPTS
rw
TAMP3TRG
rw
TAMP3E
rw
TAMP2TRG
rw
TAMP2E
rw
TAMPIE
rw
TAMP1TRG
rw
TAMP1E
rw
Toggle Fields.

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMP3E

Bit 5: Tamper 3 detection enable.

TAMP3TRG

Bit 6: Active level for tamper 3.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1IE

Bit 16: Tamper 1 interrupt enable.

TAMP1NOERASE

Bit 17: Tamper 1 no erase.

TAMP1MF

Bit 18: Tamper 1 mask flag.

TAMP2IE

Bit 19: Tamper 2 interrupt enable.

TAMP2NOERASE

Bit 20: Tamper 2 no erase.

TAMP2MF

Bit 21: Tamper 2 mask flag.

TAMP3IE

Bit 22: Tamper 3 interrupt enable.

TAMP3NOERASE

Bit 23: Tamper 3 no erase.

TAMP3MF

Bit 24: Tamper 3 mask flag.

ALRMASSR

alarm A sub second register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRMBSSR

alarm B sub second register

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

OR

option register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_OUT_RMP
rw
RTC_ALARM_TYPE
rw
Toggle Fields.

RTC_ALARM_TYPE

Bit 0: RTC_ALARM on PC13 output type.

RTC_OUT_RMP

Bit 1: RTC_OUT remap.

BKP%sR

backup register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle Fields.

BKP

Bits 0-31: BKP.

SAI1

0x40015400: Serial audio interface

42/51 fields covered. Toggle Registers.

CR1

AConfiguration register 1

Offset: 0x0, reset: 0x00000040, access: read-write

11/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle Fields.

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: Master clock generator is enabled
1: NoDiv: No divider used in the clock generator (in this case Master Clock Divider bit has no effect)

MCKDIV

Bits 20-23: Master clock divider.

CR2

AConfiguration register 2

Offset: 0x4, reset: 0x00000000, access: read-write

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECN
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
rw
FTH
rw
Toggle Fields.

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR

AFRCR

Offset: 0x8, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle Fields.

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR

ASlot register

Offset: 0xC, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle Fields.

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM

AInterrupt mask register2

Offset: 0x10, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle Fields.

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR

AStatus register

Offset: 0x14, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
rw
AFSDET
rw
CNRDY
rw
FREQ
rw
WCKCFG
rw
MUTEDET
rw
OVRUDR
rw
Toggle Fields.

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR

AClear flag register

Offset: 0x18, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
rw
CAFSDET
rw
CCNRDY
rw
CWCKCFG
rw
CMUTEDET
rw
COVRUDR
rw
Toggle Fields.

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR

AData register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle Fields.

DATA

Bits 0-31: Data.

SCB

0xE000ED00: System control block

5/74 fields covered. Toggle Registers.

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Implementer
r
Variant
r
Constant
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PartNo
r
Revision
r
Toggle Fields.

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NMIPENDSET
rw
PENDSVSET
rw
PENDSVCLR
rw
PENDSTSET
rw
PENDSTCLR
rw
ISRPENDING
rw
VECTPENDING
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTPENDING
rw
RETTOBASE
rw
VECTACTIVE
rw
Toggle Fields.

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TBLOFF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBLOFF
rw
Toggle Fields.

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VECTKEYSTAT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENDIANESS
rw
PRIGROUP
rw
SYSRESETREQ
rw
VECTCLRACTIVE
rw
VECTRESET
rw
Toggle Fields.

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEVEONPEND
rw
SLEEPDEEP
rw
SLEEPONEXIT
rw
Toggle Fields.

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKALIGN
rw
BFHFNMIGN
rw
DIV_0_TRP
rw
UNALIGN__TRP
rw
USERSETMPEND
rw
NONBASETHRDENA
rw
Toggle Fields.

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_5
rw
PRI_4
rw
Toggle Fields.

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRI_15
rw
PRI_14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle Fields.

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USGFAULTENA
rw
BUSFAULTENA
rw
MEMFAULTENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SVCALLPENDED
rw
BUSFAULTPENDED
rw
MEMFAULTPENDED
rw
USGFAULTPENDED
rw
SYSTICKACT
rw
PENDSVACT
rw
MONITORACT
rw
SVCALLACT
rw
USGFAULTACT
rw
BUSFAULTACT
rw
MEMFAULTACT
rw
Toggle Fields.

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVBYZERO
rw
UNALIGNED
rw
NOCP
rw
INVPC
rw
INVSTATE
rw
UNDEFINSTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFARVALID
rw
LSPERR
rw
STKERR
rw
UNSTKERR
rw
IMPRECISERR
rw
PRECISERR
rw
IBUSERR
rw
MMARVALID
rw
MLSPERR
rw
MSTKERR
rw
MUNSTKERR
rw
IACCVIOL
rw
Toggle Fields.

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEBUG_VT
rw
FORCED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VECTTBL
rw
Toggle Fields.

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMFAR
rw
Toggle Fields.

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BFAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BFAR
rw
Toggle Fields.

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMPDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMPDEF
rw
Toggle Fields.

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xE000E008: System control block ACTLR

0/5 fields covered. Toggle Registers.

ACTRL

Auxiliary control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISOOFP
rw
DISFPCA
rw
DISFOLD
rw
DISDEFWBUF
rw
DISMCYCINT
rw
Toggle Fields.

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SDMMC

0x40012800: Secure digital input/output interface

31/98 fields covered. Toggle Registers.

POWER

power control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRCTRL
rw
Toggle Fields.

PWRCTRL

Bits 0-1: PWRCTRL.

CLKCR

SDI clock control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HWFC_EN
rw
NEGEDGE
rw
WIDBUS
rw
BYPASS
rw
PWRSAV
rw
CLKEN
rw
CLKDIV
rw
Toggle Fields.

CLKDIV

Bits 0-7: Clock divide factor.

CLKEN

Bit 8: Clock enable bit.

PWRSAV

Bit 9: Power saving configuration bit.

BYPASS

Bit 10: Clock divider bypass enable bit.

WIDBUS

Bits 11-12: Wide bus mode enable bit.

NEGEDGE

Bit 13: SDIO_CK dephasing selection bit.

HWFC_EN

Bit 14: HW Flow Control enable.

ARG

argument register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle Fields.

CMDARG

Bits 0-31: Command argument.

CMD

command register

Offset: 0xC, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CE_ATACMD
rw
nIEN
rw
ENCMDcompl
rw
SDIOSuspend
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDINDEX
rw
Toggle Fields.

CMDINDEX

Bits 0-5: Command index.

WAITRESP

Bits 6-7: Wait for response bits.

WAITINT

Bit 8: CPSM waits for interrupt request.

WAITPEND

Bit 9: CPSM Waits for ends of data transfer (CmdPend internal signal).

CPSMEN

Bit 10: Command path state machine (CPSM) Enable bit.

SDIOSuspend

Bit 11: SD I/O suspend command.

ENCMDcompl

Bit 12: Enable CMD completion.

nIEN

Bit 13: not Interrupt Enable.

CE_ATACMD

Bit 14: CE-ATA command.

RESPCMD

command response register

Offset: 0x10, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle Fields.

RESPCMD

Bits 0-5: Response command index.

RESP1

response 1..4 register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle Fields.

CARDSTATUS1

Bits 0-31: see Table 132.

RESP2

response 1..4 register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle Fields.

CARDSTATUS2

Bits 0-31: see Table 132.

RESP3

response 1..4 register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle Fields.

CARDSTATUS3

Bits 0-31: see Table 132.

RESP4

response 1..4 register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle Fields.

CARDSTATUS4

Bits 0-31: see Table 132.

DTIMER

data timer register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle Fields.

DATATIME

Bits 0-31: Data timeout period.

DLEN

data length register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle Fields.

DATALENGTH

Bits 0-24: Data length value.

DCTRL

data control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DMAEN
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle Fields.

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: Data transfer direction selection.

DTMODE

Bit 2: Data transfer mode selection 1: Stream or SDIO multibyte data transfer.

DMAEN

Bit 3: DMA enable bit.

DBLOCKSIZE

Bits 4-7: Data block size.

RWSTART

Bit 8: Read wait start.

RWSTOP

Bit 9: Read wait stop.

RWMOD

Bit 10: Read wait mode.

SDIOEN

Bit 11: SD I/O enable functions.

DCOUNT

data counter register

Offset: 0x30, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle Fields.

DATACOUNT

Bits 0-24: Data count value.

STA

status register

Offset: 0x34, reset: 0x00000000, access: read-only

24/24 fields covered.

CCRCFAIL

Bit 0: Command response received (CRC check failed).

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed).

CTIMEOUT

Bit 2: Command response timeout.

DTIMEOUT

Bit 3: Data timeout.

TXUNDERR

Bit 4: Transmit FIFO underrun error.

RXOVERR

Bit 5: Received FIFO overrun error.

CMDREND

Bit 6: Command response received (CRC check passed).

CMDSENT

Bit 7: Command sent (no response required).

DATAEND

Bit 8: Data end (data counter, SDIDCOUNT, is zero).

STBITERR

Bit 9: Start bit not detected on all data signals in wide bus mode.

DBCKEND

Bit 10: Data block sent/received (CRC check passed).

CMDACT

Bit 11: Command transfer in progress.

TXACT

Bit 12: Data transmit in progress.

RXACT

Bit 13: Data receive in progress.

TXFIFOHE

Bit 14: Transmit FIFO half empty: at least 8 words can be written into the FIFO.

RXFIFOHF

Bit 15: Receive FIFO half full: there are at least 8 words in the FIFO.

TXFIFOF

Bit 16: Transmit FIFO full.

RXFIFOF

Bit 17: Receive FIFO full.

TXFIFOE

Bit 18: Transmit FIFO empty.

RXFIFOE

Bit 19: Receive FIFO empty.

TXDAVL

Bit 20: Data available in transmit FIFO.

RXDAVL

Bit 21: Data available in receive FIFO.

SDIOIT

Bit 22: SDIO interrupt received.

CEATAEND

Bit 23: CE-ATA command completion signal received for CMD61.

ICR

interrupt clear register

Offset: 0x38, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEATAENDC
rw
SDIOITC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCKENDC
rw
STBITERRC
rw
DATAENDC
rw
CMDSENTC
rw
CMDRENDC
rw
RXOVERRC
rw
TXUNDERRC
rw
DTIMEOUTC
rw
CTIMEOUTC
rw
DCRCFAILC
rw
CCRCFAILC
rw
Toggle Fields.

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit.

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit.

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit.

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit.

TXUNDERRC

Bit 4: TXUNDERR flag clear bit.

RXOVERRC

Bit 5: RXOVERR flag clear bit.

CMDRENDC

Bit 6: CMDREND flag clear bit.

CMDSENTC

Bit 7: CMDSENT flag clear bit.

DATAENDC

Bit 8: DATAEND flag clear bit.

STBITERRC

Bit 9: STBITERR flag clear bit.

DBCKENDC

Bit 10: DBCKEND flag clear bit.

SDIOITC

Bit 22: SDIOIT flag clear bit.

CEATAENDC

Bit 23: CEATAEND flag clear bit.

MASK

mask register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/24 fields covered.

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable.

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable.

CTIMEOUTIE

Bit 2: Command timeout interrupt enable.

DTIMEOUTIE

Bit 3: Data timeout interrupt enable.

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable.

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable.

CMDRENDIE

Bit 6: Command response received interrupt enable.

CMDSENTIE

Bit 7: Command sent interrupt enable.

DATAENDIE

Bit 8: Data end interrupt enable.

STBITERRIE

Bit 9: Start bit error interrupt enable.

DBCKENDIE

Bit 10: Data block end interrupt enable.

CMDACTIE

Bit 11: Command acting interrupt enable.

TXACTIE

Bit 12: Data transmit acting interrupt enable.

RXACTIE

Bit 13: Data receive acting interrupt enable.

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable.

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable.

TXFIFOFIE

Bit 16: Tx FIFO full interrupt enable.

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable.

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable.

RXFIFOEIE

Bit 19: Rx FIFO empty interrupt enable.

TXDAVLIE

Bit 20: Data available in Tx FIFO interrupt enable.

RXDAVLIE

Bit 21: Data available in Rx FIFO interrupt enable.

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable.

CEATAENDIE

Bit 23: CE-ATA command completion signal received interrupt enable.

FIFOCNT

FIFO counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOCOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOCOUNT
r
Toggle Fields.

FIFOCOUNT

Bits 0-23: Remaining number of words to be written to or read from the FIFO.

FIFO

data FIFO register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFOData
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOData
rw
Toggle Fields.

FIFOData

Bits 0-31: Receive and transmit FIFO data.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

10/39 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

10/39 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

SPI3

0x40003C00: Serial peripheral interface/Inter-IC sound

10/39 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
DFF
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x0002, access: Unspecified

8/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
rw
TXE
r
RXNE
r
Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x0007, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

STK

0xE000E010: SysTick timer

0/9 fields covered. Toggle Registers.

CTRL

SysTick control and status register

Offset: 0x0, reset: 0X00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNTFLAG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKSOURCE
rw
TICKINT
rw
ENABLE
rw
Toggle Fields.

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RELOAD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle Fields.

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRENT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRENT
rw
Toggle Fields.

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NOREF
rw
SKEW
rw
TENMS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TENMS
rw
Toggle Fields.

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SWPMI1

0x40008800: Single Wire Protocol Master Interface

13/38 fields covered. Toggle Registers.

CR

SWPMI Configuration/Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEACT
rw
SWPME
rw
LPBK
rw
TXMODE
rw
RXMODE
rw
TXDMA
rw
RXDMA
rw
Toggle Fields.

RXDMA

Bit 0: Reception DMA enable.

TXDMA

Bit 1: Transmission DMA enable.

RXMODE

Bit 2: Reception buffering mode.

TXMODE

Bit 3: Transmission buffering mode.

LPBK

Bit 4: Loopback mode enable.

SWPME

Bit 5: Single wire protocol master interface enable.

DEACT

Bit 10: Single wire protocol master interface deactivate.

BRR

SWPMI Bitrate register

Offset: 0x4, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR
rw
Toggle Fields.

BR

Bits 0-5: Bitrate prescaler.

ISR

SWPMI Interrupt and Status register

Offset: 0xC, reset: 0x000002C2, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEACTF
r
SUSP
r
SRF
r
TCF
r
TXE
r
RXNE
r
TXUNRF
r
RXOVRF
r
RXBERF
r
TXBEF
r
RXBFF
r
Toggle Fields.

RXBFF

Bit 0: Receive buffer full flag.

TXBEF

Bit 1: Transmit buffer empty flag.

RXBERF

Bit 2: Receive CRC error flag.

RXOVRF

Bit 3: Receive overrun error flag.

TXUNRF

Bit 4: Transmit underrun error flag.

RXNE

Bit 5: Receive data register not empty.

TXE

Bit 6: Transmit data register empty.

TCF

Bit 7: Transfer complete flag.

SRF

Bit 8: Slave resume flag.

SUSP

Bit 9: SUSPEND flag.

DEACTF

Bit 10: DEACTIVATED flag.

ICR

SWPMI Interrupt Flag Clear register

Offset: 0x10, reset: 0x00000000, access: write-only

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSRF
w
CTCF
w
CTXUNRF
w
CRXOVRF
w
CRXBERF
w
CTXBEF
w
CRXBFF
w
Toggle Fields.

CRXBFF

Bit 0: Clear receive buffer full flag.

CTXBEF

Bit 1: Clear transmit buffer empty flag.

CRXBERF

Bit 2: Clear receive CRC error flag.

CRXOVRF

Bit 3: Clear receive overrun error flag.

CTXUNRF

Bit 4: Clear transmit underrun error flag.

CTCF

Bit 7: Clear transfer complete flag.

CSRF

Bit 8: Clear slave resume flag.

IER

SWPMI Interrupt Enable register

Offset: 0x14, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRIE
rw
TCIE
rw
TIE
rw
RIE
rw
TXUNRIE
rw
RXOVRIE
rw
RXBERIE
rw
TXBEIE
rw
RXBFIE
rw
Toggle Fields.

RXBFIE

Bit 0: Receive buffer full interrupt enable.

TXBEIE

Bit 1: Transmit buffer empty interrupt enable.

RXBERIE

Bit 2: Receive CRC error interrupt enable.

RXOVRIE

Bit 3: Receive overrun error interrupt enable.

TXUNRIE

Bit 4: Transmit underrun error interrupt enable.

RIE

Bit 5: Receive interrupt enable.

TIE

Bit 6: Transmit interrupt enable.

TCIE

Bit 7: Transmit complete interrupt enable.

SRIE

Bit 8: Slave resume interrupt enable.

RFL

SWPMI Receive Frame Length register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFL
r
Toggle Fields.

RFL

Bits 0-4: Receive frame length.

TDR

SWPMI Transmit data register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TD
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TD
w
Toggle Fields.

TD

Bits 0-31: Transmit data.

RDR

SWPMI Receive data register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD
r
Toggle Fields.

RD

Bits 0-31: received data.

SYSCFG

0x40010000: System configuration controller

1/69 fields covered. Toggle Registers.

MEMRMP

memory remap register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FB_MODE
rw
QFS
rw
MEM_MODE
rw
Toggle Fields.

MEM_MODE

Bits 0-2: Memory mapping selection.

QFS

Bit 3: QUADSPI memory mapping swap.

FB_MODE

Bit 8: Flash Bank mode selection.

CFGR1

configuration register 1

Offset: 0x4, reset: 0x7C000001, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPU_IE
rw
I2C3_FMP
rw
I2C2_FMP
rw
I2C1_FMP
rw
I2C_PB9_FMP
rw
I2C_PB8_FMP
rw
I2C_PB7_FMP
rw
I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOSTEN
rw
FWDIS
rw
Toggle Fields.

FWDIS

Bit 0: Firewall disable.

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

FPU_IE

Bits 26-31: Floating Point Unit interrupts enable bits.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3
rw
EXTI2
rw
EXTI1
rw
EXTI0
rw
Toggle Fields.

EXTI0

Bits 0-2: EXTI 0 configuration bits.

EXTI1

Bits 4-6: EXTI 1 configuration bits.

EXTI2

Bits 8-10: EXTI 2 configuration bits.

EXTI3

Bits 12-14: EXTI 3 configuration bits.

EXTICR2

external interrupt configuration register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7
rw
EXTI6
rw
EXTI5
rw
EXTI4
rw
Toggle Fields.

EXTI4

Bits 0-2: EXTI 4 configuration bits.

EXTI5

Bits 4-6: EXTI 5 configuration bits.

EXTI6

Bits 8-10: EXTI 6 configuration bits.

EXTI7

Bits 12-14: EXTI 7 configuration bits.

EXTICR3

external interrupt configuration register 3

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11
rw
EXTI10
rw
EXTI9
rw
EXTI8
rw
Toggle Fields.

EXTI8

Bits 0-2: EXTI 8 configuration bits.

EXTI9

Bits 4-6: EXTI 9 configuration bits.

EXTI10

Bits 8-10: EXTI 10 configuration bits.

EXTI11

Bits 12-14: EXTI 11 configuration bits.

EXTICR4

external interrupt configuration register 4

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15
rw
EXTI14
rw
EXTI13
rw
EXTI12
rw
Toggle Fields.

EXTI12

Bits 0-2: EXTI12 configuration bits.

EXTI13

Bits 4-6: EXTI13 configuration bits.

EXTI14

Bits 8-10: EXTI14 configuration bits.

EXTI15

Bits 12-14: EXTI15 configuration bits.

SCSR

SCSR

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r
SRAM2ER
rw
Toggle Fields.

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

CFGR2

CFGR2

Offset: 0x1C, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw
ECCL
w
PVDL
w
SPL
w
CLL
w
Toggle Fields.

CLL

Bit 0: OCKUP (Hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SWPR

SWPR

Offset: 0x20, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP
w
P30WP
w
P29WP
w
P28WP
w
P27WP
w
P26WP
w
P25WP
w
P24WP
w
P23WP
w
P22WP
w
P21WP
w
P20WP
w
P19WP
w
P18WP
w
P17WP
w
P16WP
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP
w
P14WP
w
P13WP
w
P12WP
w
P11WP
w
P10WP
w
P9WP
w
P8WP
w
P7WP
w
P6WP
w
P5WP
w
P4WP
w
P3WP
w
P2WP
w
P1WP
w
P0WP
w
Toggle Fields.

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SKR

SKR

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle Fields.

KEY

Bits 0-7: SRAM2 write protection key for software erase.

TIM1

0x40012C00: Advanced-timers

77/157 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw
OIS3N
rw
OIS3
rw
OIS2N
rw
OIS2
rw
OIS1N
rw
OIS1
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4P
rw
CC4E
rw
CC3NP
rw
CC3NE
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2NE
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: Disabled: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, reset: 0x0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
ETR_ADC3_RMP
rw
ETR_ADC1_RMP
rw
Toggle Fields.

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

ETR_ADC3_RMP

Bits 2-3: External trigger remap on ADC3 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M_bit3
rw
OC5M_bit3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw
OC6M
rw
OC6PE
rw
OC6FE
rw
OC5CE
rw
OC5M
rw
OC5PE
rw
OC5FE
rw
Toggle Fields.

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_bit3

Bits 16-18: Output Compare 5 mode bit 3.

OC6M_bit3

Bit 24: Output Compare 6 mode bit 3.

CCR5

capture/compare register 4

Offset: 0x58, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare value.

OR2

DMA address for full transfer

Offset: 0x60, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, reset: 0x00000001, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DFBK0E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle Fields.

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM15

0x40014000: General purpose timers

10/62 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw
OIS1
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

TIM16

0x40014400: General purpose timers

20/70 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

6/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: NotStopped: Not stopped at update event
1: Stopped: Counter stops counting at next update event

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw
OIS1
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Default: Capture/compare are updated only by setting the COMG bit
1: WithRisingEdge: Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS1

Bit 8: Output Idle state 1.

Allowed values:
0: Low: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
1: High: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0

OIS1N

Bit 9: Output Idle state 1.

Allowed values:
0: Low: OC1N=0 after a dead-time when MOE=0
1: High: OC1N=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

5/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC1DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CC1 interrupt disabled
1: Enabled: CC1 interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CC1 DMA request disabled
1: Enabled: CC1 DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw
BIF
rw
TIF
rw
COMIF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw
CC1NE
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle Fields.

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK1E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK1E

Bit 8: BRK DFSDM_BREAK1 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM2

0x40000000: General-purpose-timers

74/100 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-31: Counter value.

Allowed values: 0-4294967295

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0-4294967295

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-31: Capture/Compare 1 value.

Allowed values: 0-4294967295

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR_RMP
rw
Toggle Fields.

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM3

0x40000400: General-purpose-timers

74/103 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: The UG bit from the TIMx_EGR register is used as trigger output
1: Enable: The counter enable signal, CNT_EN, is used as trigger output
2: Update: The update event is selected as trigger output
3: ComparePulse: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
4: CompareOC1: OC1REF signal is used as trigger output
5: CompareOC2: OC2REF signal is used as trigger output
6: CompareOC3: OC3REF signal is used as trigger output
7: CompareOC4: OC4REF signal is used as trigger output

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

Allowed values:
0: Disabled: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
1: Encoder_Mode_1: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
2: Encoder_Mode_2: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
3: Encoder_Mode_3: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.
4: Reset_Mode: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.
5: Gated_Mode: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
6: Trigger_Mode: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.
7: Ext_Clock_Mode: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

TS

Bits 4-6: Trigger selection.

Allowed values:
0: ITR0: Internal Trigger 0 (ITR0)
1: ITR1: Internal Trigger 1 (ITR1)
2: ITR2: Internal Trigger 2 (ITR2)
4: TI1F_ED: TI1 Edge Detector (TI1F_ED)
5: TI1FP1: Filtered Timer Input 1 (TI1FP1)
6: TI2FP2: Filtered Timer Input 2 (TI2FP2)
7: ETRF: External Trigger input (ETRF)

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

12/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC4DE
rw
CC3DE
rw
CC2DE
rw
CC1DE
rw
UDE
rw
TIE
rw
CC4IE
rw
CC3IE
rw
CC2IE
rw
CC1IE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4OF
rw
CC3OF
rw
CC2OF
rw
CC1OF
rw
TIF
rw
CC4IF
rw
CC3IF
rw
CC2IF
rw
CC1IF
rw
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

Allowed values:
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC4G
w
CC3G
w
CC2G
w
CC1G
w
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC1G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC2G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC3G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC4G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw
IC2PSC
rw
CC2S
rw
IC1F
rw
IC1PSC
rw
CC1S
rw
Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

Allowed values: 0-15

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw
IC4PSC
rw
CC4S
rw
IC3F
rw
IC3PSC
rw
CC3S
rw
Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC3PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values: 0-3

IC3F

Bits 4-7: Input capture 3 filter.

Allowed values: 0-15

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC4PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values: 0-3

IC4F

Bits 12-15: Input capture 4 filter.

Allowed values: 0-15

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw
CC4P
rw
CC4E
rw
CC3NP
rw
CC3P
rw
CC3E
rw
CC2NP
rw
CC2P
rw
CC2E
rw
CC1NP
rw
CC1P
rw
CC1E
rw
Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Counter value.

Allowed values: 0-65535

CNT_H

Bits 16-31: High counter value (TIM2 only).

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0-65535

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR%s

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR1_H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle Fields.

CCR

Bits 0-15: Capture/Compare 1 value.

Allowed values: 0-65535

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle Fields.

DBA

Bits 0-4: DMA base address.

Allowed values: 0-31

DBL

Bits 8-12: DMA burst length.

Allowed values: 0-18

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR_RMP
rw
Toggle Fields.

ETR_RMP

Bits 0-2: Timer2 ETR remap.

TI4_RMP

Bits 3-4: Internal trigger.

TIM6

0x40001000: Basic-timers

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65535

TIM7

0x40001400: Basic-timers

13/13 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle Fields.

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle Fields.

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle Fields.

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
rw
Toggle Fields.

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: Clear: No update occurred
1: UpdatePending: Update interrupt pending.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle Fields.

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle Fields.

CNT

Bits 0-15: Low counter value.

Allowed values: 0-65535

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle Fields.

PSC

Bits 0-15: Prescaler value.

Allowed values: 0-65535

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle Fields.

ARR

Bits 0-15: Low Auto-reload value.

Allowed values: 0-65535

TSC

0x40024000: Touch sensing controller

9/163 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw
CTPL
rw
SSD
rw
SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw
PGPSC
rw
MCV
rw
IODEF
rw
SYNCPOL
rw
AM
rw
START
rw
TSCE
rw
Toggle Fields.

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw
EOAIE
rw
Toggle Fields.

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw
EOAIC
rw
Toggle Fields.

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw
EOAF
rw
Toggle Fields.

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw
G8_IO3
rw
G8_IO2
rw
G8_IO1
rw
G7_IO4
rw
G7_IO3
rw
G7_IO2
rw
G7_IO1
rw
G6_IO4
rw
G6_IO3
rw
G6_IO2
rw
G6_IO1
rw
G5_IO4
rw
G5_IO3
rw
G5_IO2
rw
G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw
G4_IO3
rw
G4_IO2
rw
G4_IO1
rw
G3_IO4
rw
G3_IO3
rw
G3_IO2
rw
G3_IO1
rw
G2_IO4
rw
G2_IO3
rw
G2_IO2
rw
G2_IO1
rw
G1_IO4
rw
G1_IO3
rw
G1_IO2
rw
G1_IO1
rw
Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw
G8_IO3
rw
G8_IO2
rw
G8_IO1
rw
G7_IO4
rw
G7_IO3
rw
G7_IO2
rw
G7_IO1
rw
G6_IO4
rw
G6_IO3
rw
G6_IO2
rw
G6_IO1
rw
G5_IO4
rw
G5_IO3
rw
G5_IO2
rw
G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw
G4_IO3
rw
G4_IO2
rw
G4_IO1
rw
G3_IO4
rw
G3_IO3
rw
G3_IO2
rw
G3_IO1
rw
G2_IO4
rw
G2_IO3
rw
G2_IO2
rw
G2_IO1
rw
G1_IO4
rw
G1_IO3
rw
G1_IO2
rw
G1_IO1
rw
Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw
G8_IO3
rw
G8_IO2
rw
G8_IO1
rw
G7_IO4
rw
G7_IO3
rw
G7_IO2
rw
G7_IO1
rw
G6_IO4
rw
G6_IO3
rw
G6_IO2
rw
G6_IO1
rw
G5_IO4
rw
G5_IO3
rw
G5_IO2
rw
G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw
G4_IO3
rw
G4_IO2
rw
G4_IO1
rw
G3_IO4
rw
G3_IO3
rw
G3_IO2
rw
G3_IO1
rw
G2_IO4
rw
G2_IO3
rw
G2_IO2
rw
G2_IO1
rw
G1_IO4
rw
G1_IO3
rw
G1_IO2
rw
G1_IO1
rw
Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4
rw
G8_IO3
rw
G8_IO2
rw
G8_IO1
rw
G7_IO4
rw
G7_IO3
rw
G7_IO2
rw
G7_IO1
rw
G6_IO4
rw
G6_IO3
rw
G6_IO2
rw
G6_IO1
rw
G5_IO4
rw
G5_IO3
rw
G5_IO2
rw
G5_IO1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4
rw
G4_IO3
rw
G4_IO2
rw
G4_IO1
rw
G3_IO4
rw
G3_IO3
rw
G3_IO2
rw
G3_IO1
rw
G2_IO4
rw
G2_IO3
rw
G2_IO2
rw
G2_IO1
rw
G1_IO4
rw
G1_IO3
rw
G1_IO2
rw
G1_IO1
rw
Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r
G7S
r
G6S
r
G5S
r
G4S
r
G3S
r
G2S
r
G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw
G7E
rw
G6E
rw
G5E
rw
G4E
rw
G3E
rw
G2E
rw
G1E
rw
Toggle Fields.

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG%sCR

I/O group x counter register

Offset: 0x34, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle Fields.

CNT

Bits 0-13: Counter value.

UART4

0x40004C00: Universal synchronous asynchronous receiver transmitter

104/104 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0-31

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0-65535

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GT

Bits 8-15: Guard time value.

Allowed values: 0-255

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BLEN

Bits 24-31: Block Length.

Allowed values: 0-255

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCCF
w
IDLECF
w
ORECF
w
NCF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

Allowed values: 0-255

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

Allowed values: 0-255

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

104/104 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0-31

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0-65535

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GT

Bits 8-15: Guard time value.

Allowed values: 0-255

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BLEN

Bits 24-31: Block Length.

Allowed values: 0-255

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCCF
w
IDLECF
w
ORECF
w
NCF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

Allowed values: 0-255

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

Allowed values: 0-255

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

104/104 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0-31

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-15: DIV_Mantissa.

Allowed values: 0-65535

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GT

Bits 8-15: Guard time value.

Allowed values: 0-255

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BLEN

Bits 24-31: Block Length.

Allowed values: 0-255

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCCF
w
IDLECF
w
ORECF
w
NCF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

Allowed values: 0-255

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

Allowed values: 0-255

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

107/107 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle Fields.

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0-31

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0-31

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

18/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
Toggle Fields.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0-255

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGTIE
rw
UCESM
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle Fields.

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0-7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

UCESM

Bit 23: USART Clock Enable in Stop mode.

Allowed values:
0: Disabled: USART clock is disabled in STOP mode
1: Enabled: USART clock is enabled in STOP mode

TCBGTIE

Bit 24: Transmission complete before guard time interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever TCBGT=1 in the ISR register

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle Fields.

BRR

Bits 0-11: USARTDIV.

Allowed values: 0-65535

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle Fields.

PSC

Bits 0-7: Prescaler value.

Allowed values: 0-255

GT

Bits 8-15: Guard time value.

Allowed values: 0-255

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0-16777215

BLEN

Bits 24-31: Block Length.

Allowed values: 0-255

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

23/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TCBGT

Bit 25: Transmission complete before guard time completion.

Allowed values:
0: NotCompleted: Transmission not completed
1: Completed: Transmission has completed

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w
CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOBCF
w
RTOCF
w
CTSCF
w
LBDCF
w
TCCF
w
IDLECF
w
ORECF
w
NCF
w
FECF
w
PECF
w
Toggle Fields.

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle Fields.

RDR

Bits 0-8: Receive data value.

Allowed values: 0-255

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle Fields.

TDR

Bits 0-8: Transmit data value.

Allowed values: 0-255

USB

0x40006800: Universal serial bus full-speed device interface

51/57 fields covered. Toggle Registers.

EP%sR

endpoint 0 register

Offset: 0x0, reset: 0x00000000, access: read-write

4/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle Fields.

EA

Bits 0-3: Endpoint address.

Allowed values: 0-15

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

Allowed values:
0: Disabled: all transmission requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all transmission requests result in a STALL handshake
2: Nak: the endpoint is naked and all transmission requests result in a NAK handshake
3: Valid: this endpoint is enabled for transmission

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

Allowed values:
0: Bulk: Bulk endpoint
1: Control: Control endpoint
2: Iso: Iso endpoint
3: Interrupt: Interrupt endpoint

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

Allowed values:
0: Disabled: all reception requests addressed to this endpoint are ignored
1: Stall: the endpoint is stalled and all reception requests result in a STALL handshake
2: Nak: the endpoint is naked and all reception requests result in a NAK handshake
3: Valid: this endpoint is enabled for reception

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, reset: 0x00000003, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRM
rw
PMAOVRM
rw
ERRM
rw
WKUPM
rw
SUSPM
rw
RESETM
rw
SOFM
rw
ESOFM
rw
L1REQM
rw
L1RESUME
rw
RESUME
rw
FSUSP
rw
LPMODE
rw
PDWN
rw
FRES
rw
Toggle Fields.

FRES

Bit 0: Force USB Reset.

Allowed values:
0: NoReset: Clear USB reset
1: Reset: Force a reset of the USB peripheral, exactly like a RESET signaling on the USB

PDWN

Bit 1: Power down.

Allowed values:
0: Disabled: No power down
1: Enabled: Enter power down mode

LPMODE

Bit 2: Low-power mode.

Allowed values:
0: Disabled: No low-power mode
1: Enabled: Enter low-power mode

FSUSP

Bit 3: Force suspend.

Allowed values:
0: NoEffect: No effect
1: Suspend: Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected

RESUME

Bit 4: Resume request.

Allowed values:
1: Requested: Resume requested

L1RESUME

Bit 5: LPM L1 Resume request.

Allowed values:
1: Requested: LPM L1 request requested

L1REQM

Bit 7: LPM L1 state request interrupt mask.

Allowed values:
0: Disabled: L1REQ Interrupt disabled
1: Enabled: L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ESOFM

Bit 8: Expected start of frame interrupt mask.

Allowed values:
0: Disabled: ESOF Interrupt disabled
1: Enabled: ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SOFM

Bit 9: Start of frame interrupt mask.

Allowed values:
0: Disabled: SOF Interrupt disabled
1: Enabled: SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

RESETM

Bit 10: USB reset interrupt mask.

Allowed values:
0: Disabled: RESET Interrupt disabled
1: Enabled: RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

SUSPM

Bit 11: Suspend mode interrupt mask.

Allowed values:
0: Disabled: Suspend Mode Request SUSP Interrupt disabled
1: Enabled: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

WKUPM

Bit 12: Wakeup interrupt mask.

Allowed values:
0: Disabled: WKUP Interrupt disabled
1: Enabled: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ERRM

Bit 13: Error interrupt mask.

Allowed values:
0: Disabled: ERR Interrupt disabled
1: Enabled: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

Allowed values:
0: Disabled: PMAOVR Interrupt disabled
1: Enabled: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

CTRM

Bit 15: Correct transfer interrupt mask.

Allowed values:
0: Disabled: Correct Transfer (CTR) Interrupt disabled
1: Enabled: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set

ISTR

interrupt status register

Offset: 0x44, reset: 0x00000000, access: Unspecified

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
r
PMAOVR
rw
ERR
rw
WKUP
rw
SUSP
rw
RESET
rw
SOF
rw
ESOF
rw
L1REQ
rw
DIR
r
EP_ID
r
Toggle Fields.

EP_ID

Bits 0-3: Endpoint Identifier.

Allowed values: 0-15

DIR

Bit 4: Direction of transaction.

Allowed values:
0: To: data transmitted by the USB peripheral to the host PC
1: From: data received by the USB peripheral from the host PC

L1REQ

Bit 7: LPM L1 state request.

Allowed values:
1: Received: LPM command to enter the L1 state is successfully received and acknowledged

ESOF

Bit 8: Expected start frame.

Allowed values:
1: ExpectedStartOfFrame: an SOF packet is expected but not received

SOF

Bit 9: start of frame.

Allowed values:
1: StartOfFrame: beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus

RESET

Bit 10: reset request.

Allowed values:
1: Reset: peripheral detects an active USB RESET signal at its inputs

SUSP

Bit 11: Suspend mode request.

Allowed values:
1: Suspend: no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus

WKUP

Bit 12: Wakeup.

Allowed values:
1: Wakeup: activity is detected that wakes up the USB peripheral

ERR

Bit 13: Error.

Allowed values:
1: Error: One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred

PMAOVR

Bit 14: Packet memory area over / underrun.

Allowed values:
1: Overrun: microcontroller has not been able to respond in time to an USB memory request

CTR

Bit 15: Correct transfer.

Allowed values:
1: Completed: endpoint has successfully completed a transaction

FNR

frame number register

Offset: 0x48, reset: 0x0000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r
RXDM
r
LCK
r
LSOF
r
FN
r
Toggle Fields.

FN

Bits 0-10: Frame number.

Allowed values: 0-2047

LSOF

Bits 11-12: Lost SOF.

Allowed values: 0-3

LCK

Bit 13: Locked.

Allowed values:
1: Locked: the frame timer remains in this state until an USB reset or USB suspend event occurs

RXDM

Bit 14: Receive data - line status.

Allowed values:
1: Received: received data minus upstream port data line

RXDP

Bit 15: Receive data + line status.

Allowed values:
1: Received: received data plus upstream port data line

DADDR

device address

Offset: 0x4C, reset: 0x0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw
ADD
rw
Toggle Fields.

ADD

Bits 0-6: Device address.

Allowed values: 0-127

EF

Bit 7: Enable function.

Allowed values:
0: Disabled: USB device disabled
1: Enabled: USB device enabled

BTABLE

Buffer table address

Offset: 0x50, reset: 0x0000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle Fields.

BTABLE

Bits 3-15: Buffer table.

Allowed values: 0-8191

LPMCSR

LPM control and status register

Offset: 0x54, reset: 0x0000, access: Unspecified

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BESL
r
REMWAKE
r
LPMACK
rw
LPMEN
rw
Toggle Fields.

LPMEN

Bit 0: LPM support enable.

Allowed values:
0: Disabled: enable the LPM support within the USB device
1: Enabled: no LPM transactions are handled

LPMACK

Bit 1: LPM Token acknowledge enable.

Allowed values:
0: Nyet: the valid LPM Token will be NYET
1: Ack: the valid LPM Token will be ACK

REMWAKE

Bit 3: bRemoteWake value.

BESL

Bits 4-7: BESL value.

Allowed values: 0-15

BCDR

Battery charging detector

Offset: 0x58, reset: 0x0000, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU
rw
PS2DET
r
SDET
r
PDET
r
DCDET
r
SDEN
rw
PDEN
rw
DCDEN
rw
BCDEN
rw
Toggle Fields.

BCDEN

Bit 0: Battery charging detector.

Allowed values:
0: Disabled: disable the BCD support
1: Enabled: enable the BCD support within the USB device

DCDEN

Bit 1: Data contact detection.

Allowed values:
0: Disabled: Data contact detection (DCD) mode disabled
1: Enabled: Data contact detection (DCD) mode enabled

PDEN

Bit 2: Primary detection.

Allowed values:
0: Disabled: Primary detection (PD) mode disabled
1: Enabled: Primary detection (PD) mode enabled

SDEN

Bit 3: Secondary detection.

Allowed values:
0: Disabled: Secondary detection (SD) mode disabled
1: Enabled: Secondary detection (SD) mode enabled

DCDET

Bit 4: Data contact detection.

Allowed values:
0: NotDetected: data lines contact not detected
1: Detected: data lines contact detected

PDET

Bit 5: Primary detection.

Allowed values:
0: NoBCD: no BCD support detected
1: BCD: BCD support detected

SDET

Bit 6: Secondary detection.

Allowed values:
0: CDP: CDP detected
1: DCP: DCP detected

PS2DET

Bit 7: DM pull-up detection status.

Allowed values:
0: Normal: Normal port detected
1: PS2: PS2 port or proprietary charger detected

DPPU

Bit 15: DP pull-up control.

Allowed values:
0: Disabled: signalize disconnect to the host when needed by the user software
1: Enabled: enable the embedded pull-up on the DP line

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered. Toggle Registers.

CSR

VREF control and status register

Offset: 0x0, reset: 0x00000002, access: Unspecified

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r
VRS
rw
HIZ
rw
ENVR
rw
Toggle Fields.

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle Fields.

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002C00: System window watchdog

6/6 fields covered. Toggle Registers.

CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB).

Allowed values: 0-127

WDGA

Bit 7: Activation bit.

Allowed values:
0: Disabled: Watchdog disabled
1: Enabled: Watchdog enabled

CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw
WDGTB
rw
W
rw
Toggle Fields.

W

Bits 0-6: 7-bit window value.

Allowed values: 0-127

WDGTB

Bits 7-8: Timer base.

Allowed values:
0: Div1: Counter clock (PCLK1 div 4096) div 1
1: Div2: Counter clock (PCLK1 div 4096) div 2
2: Div4: Counter clock (PCLK1 div 4096) div 4
3: Div8: Counter clock (PCLK1 div 4096) div 8

EWI

Bit 9: Early wakeup interrupt.

Allowed values:
1: Enable: interrupt occurs whenever the counter reaches the value 0x40

SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.

Allowed values:
1: Pending: The EWI Interrupt Service Routine has been triggered
0: Finished: The EWI Interrupt Service Routine has been serviced